RTL Problems / Level 1 · Digital Logic Fundamentals
What You Will Learn
By solving 1-to-4 Demultiplexer, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Route a single input signal to one of four output lines based on a 2-bit select code.
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
in to out[sel] while driving all other outputs to 0. Can be implemented with bit shift assign out = in << sel; or a case(sel) statement.Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Name | Dir | Width | Description |
|---|---|---|---|
| in | input | 1 | Data input signal |
| sel | input | 2 | 2-bit line selector (00->out[0], 01->out[1], etc.) |
| out | output | 4 | 4-bit one-hot routed output |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: Strict synchronous timing aligned to posedge clk or zero-delay combinational propagation.
Synthesis Constraints: Synthesizable Verilog-2001. No # delays in synthesizable RTL.
Starter RTL Code
module top_module(
input in,
input [1:0] sel,
output [3:0] out
);
// Your code here
endmodule
Related RTL Problems in Level 1
- Wire Connection — Basic Verilog Assignments — Connect a single-bit input port directly to an output port using a continuous assignment.
- NOT Gate — Bitwise Inversion — Implement a 1-bit inverter (NOT gate). When input is 0, output is 1; when input is 1, output is 0.
- 2-Input AND Gate — Combinational Logic — Implement a 2-input AND gate whose output is 1 if and only if both inputs a and b are 1.
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Frequently Asked Questions
What does 1-to-4 Demultiplexer require?
Route a single input signal to one of four output lines based on a 2-bit select code. Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: combinational, mux, demux. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of 1-to-4 Demultiplexer to assess real-world synthesizability and race-condition awareness.