Intermediate
L2–L3
⏱️ 4–6 weeks
Combinational RTL Design
Master procedural always blocks, case statements, priority encoders, signed arithmetic, and latch-free synthesizable RTL.
Procedural Blocks & Sensitivity Lists
Master always @* and always_comb semantics for pure combinational logic.
Combinational always @*Reg types in procedural blocksSensitivity list completeness
Practice RTL Problems (1)
Case Statements & Priority Encoders
Implement parallel vs priority logic decoding using case, casex, casez and if-else ladders.
Priority encoder treesDefault case handlingSynthesized priority logic depth
Practice RTL Problems (1)
Arithmetic Logic Units (ALU)
Design parameterizable multi-operation ALUs supporting ADD, SUB, AND, OR, XOR, and SLT.
Operation opcode decodingResource sharing in add/subZero flag calculation
Practice RTL Problems (2)
Barrel Shifters & Rotators
Implement logarithmic barrel shifters and rotators for high-performance DSP data paths.
Logical shift vs arithmetic shiftCyclic rotationMultiplexer array scaling
Practice RTL Problems (2)
Seven-Segment & Display Decoders
Convert BCD and Hexadecimal nibbles to 7-segment display control lines.
Active-low cathode driveLookup table synthesisIllegal input handling
Practice RTL Problems (2)
Signed Arithmetic & Two's Complement
Understand Verilog signed types, two's complement negation, sign extension, and signed comparators.
$signed attributeBit width extension rulesSigned vs unsigned overflow
Practice RTL Problems (2)
Signed Overflow & Saturating Adders
Prevent audio/graphics wrap-around clipping using hardware saturation clamps.
Signed overflow flags (V)Clamping to MAX_INT / MIN_INTDSP arithmetic
Practice RTL Problems (2)
Population Count & Leading Zero Counters
Design parallel adder trees for bit counting (popcount) and leading zero detection.
Wallace-tree popcountPriority encoder for LZFloating-point normalization
Practice RTL Problems (2)
Parity Trees & Hamming Error Correction
Construct XOR parity generators and Hamming (7,4) single-error correction matrix decoders.
Odd/Even paritySyndrome calculationSingle-error correction (SEC)
Practice RTL Problems (2)
Latch Avoidance & Synthesis Cleanliness
Identify and eliminate inferred latches caused by incomplete if/case branching in combinational blocks.
Inferred latch hazardsDefault variable assignmentsSynthesis warning flags
Practice RTL Problems (1)
Why Master Combinational RTL Design?
Write clean, latch-free combinational logic with optimal area and timing metrics. Engineers who excel in this curriculum consistently outperform in technical interviews at semiconductor leaders such as NVIDIA, Qualcomm, Apple, and Intel because this roadmap focuses on synthesizability, edge-case assertions, and real simulation waveforms rather than purely theoretical textbook logic.
Recommended Learning Methodology
- Step 1 — Understand the Concept: Read each module's core objectives and referenced EcrioniX guide.
- Step 2 — Code the RTL: Open each practice challenge and implement
top_module matching the exact ports and timing contract.
- Step 3 — Inspect Waveforms: Run the remote cloud simulator to generate timing waveforms (VCD). Compare your signal transitions with the golden WaveDrom contract.
- Step 4 — Review Explanations: Even after passing, review the editorial notes and hardware considerations to understand ASIC synthesis tradeoffs.
Frequently Asked Questions
What tools do I need for this roadmap?
None! All simulation testbenches run in the browser using our remote Icarus Verilog runner with automated waveform generation.
Are the reference solutions accessible?
Yes. Reference solutions are protected in an expandable solution drawer. We strongly encourage attempting and simulating your own RTL first.