Digital Dice (LFSR)

Verilog problems / Sequential Design

What you must build

An LFSR-powered dice roller: advance a maximal-length 3-bit LFSR each cycle and map its output into a valid 1-6 range.

Engineers use “Digital Dice (LFSR)” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input      clk,
  input      rst,
  input      roll_en,
  output [2:0] dice_value
);

  // Your code here — 3-bit LFSR (feedback = q[2]^q[1]), seeded to 3'b001, folding 7 back to 1.

endmodule

Why this shows up in interviews

Digital Dice (LFSR) sits under Sequential Design (sequential, lfsr). Concept: A 3-bit maximal LFSR naturally cycles through the 7 nonzero values 1-7, never landing on 0. Fold the one out-of-range value back in: dice_value = (lfsr==7) ? 1 : lfsr; . Skipping that fold-back would let the circuit output an impossible "7" on a six-sided die.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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