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Part of Curriculum: Memory and FIFO Design (Module 6: Programmable Watermarks (Almost-Full / Almost-Empty))
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Level 8 Expert ★ Advanced #56 50 pts ✓ Solved

Programmable FIFO Watermark & Threshold Controller

Advanced RTL & Protocol Design · advanced-rtl, fifo-and-buffer-architecture, systemverilog, asic, fpga

Design a programmable watermark controller generating almost-full and almost-empty interrupt thresholds for DMA flow control.

Module Specification
Write a synthesizable Verilog module named top_module matching the ports below exactly.
📐 Circuit Schematic Diagram
pushalmost_full_thresh[3:0]almost_empty_thresh[3:0]almost_fullfulloccupancy[4:0]>clkrst_nPROGRAMMABLE FIFO WADIGITAL HARDWARE BLOCK
⚡ Timing & Synthesizability Constraints

Timing Contract: Clocked on posedge clk with active-low rst_n. Count increments on push, decrements on pop, holds on both.

RTL Constraints: Synthesizable Verilog-2001. No latch inference.

Objective: Implement a threshold watermark evaluator for a 16-entry buffer. Given programmable threshold inputs almost_full_thresh[3:0] and almost_empty_thresh[3:0], evaluate current occupancy count. Assert almost_full when count >= almost_full_thresh, and almost_empty when count <= almost_empty_thresh. Support concurrent push/pop with clean boundary handling.

Prerequisites: Watermark indicators, DMA burst thresholds, FIFO occupancy counters.
Port Contract
PortDirWidthDescription
clk, rst_ninput1Clock and active-low synchronous reset
push, popinput1, 1Enqueue and dequeue strobes
almost_full_thresh[3:0]input4Upper watermark threshold
almost_empty_thresh[3:0]input4Lower watermark threshold
almost_full, almost_emptyoutput1, 1Programmable watermark status indicators
full, emptyoutput1, 1Absolute capacity boundaries
occupancy[4:0]output5Exact item count (0 to 16)
Expected Waveform (Golden Timing Contract)
💡 Need Guidance? Progressive Hints (3 Levels)
Hint 1: Conceptual Direction & Hardware Primitives
Use a 5-bit register for occupancy so that it can hold values from 0 up to 16 inclusive.
Hint 2: Implementation Architecture & Approach
Extend 4-bit thresholds to 5 bits before comparing with occupancy ({1'b0, almost_full_thresh}).
Hint 3: Edge Cases, Timing & Verilog Syntax
Handle concurrent push and pop without altering the count.
🔒 Reveal Verified Reference RTL Solution (Click to expand)
⚠️ Self-Discovery Warning: Try solving and simulating first! Viewing the verified reference implementation will bypass the real debugging experience.
Verified Synthesizable RTL 
module top_module (
  input  wire       clk,
  input  wire       rst_n,
  input  wire       push,
  input  wire       pop,
  input  wire [3:0] almost_full_thresh,
  input  wire [3:0] almost_empty_thresh,
  output wire       almost_full,
  output wire       almost_empty,
  output wire       full,
  output wire       empty,
  output reg  [4:0] occupancy
);

  assign full  = (occupancy == 5'd16);
  assign empty = (occupancy == 5'd0);

  assign almost_full  = (occupancy >= {1'b0, almost_full_thresh});
  assign almost_empty = (occupancy <= {1'b0, almost_empty_thresh});

  wire valid_push = push && (!full || pop);
  wire valid_pop  = pop && !empty;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      occupancy <= 5'd0;
    end else begin
      case ({valid_push, valid_pop})
        2'b10: occupancy <= occupancy + 5'd1;
        2'b01: occupancy <= occupancy - 5'd1;
        default: ; // 2'b00 or 2'b11 -> maintain count
      endcase
    end
  end

endmodule
Verilog-2001 / SV Saved
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Simulation Timing Diagram (VCD Waveform)
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RTL Problems / Level 8 · Advanced RTL & Protocol Design

What You Will Learn

By solving Programmable FIFO Watermark & Threshold Controller, you will acquire core industry skills:

  • Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
  • Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
  • Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
  • Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design a programmable watermark controller generating almost-full and almost-empty interrupt thresholds for DMA flow control.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Objective: Implement a threshold watermark evaluator for a 16-entry buffer. Given programmable threshold inputs almost_full_thresh[3:0] and almost_empty_thresh[3:0], evaluate current occupancy count. Assert almost_full when count >= almost_full_thresh, and almost_empty when count <= almost_empty_thresh. Support concurrent push/pop with clean boundary handling.

Prerequisites: Watermark indicators, DMA burst thresholds, FIFO occupancy counters.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

PortDirWidthDescription
clk, rst_ninput1Clock and active-low synchronous reset
push, popinput1, 1Enqueue and dequeue strobes
almost_full_thresh[3:0]input4Upper watermark threshold
almost_empty_thresh[3:0]input4Lower watermark threshold
almost_full, almost_emptyoutput1, 1Programmable watermark status indicators
full, emptyoutput1, 1Absolute capacity boundaries
occupancy[4:0]output5Exact item count (0 to 16)

Timing Constraints & Synthesizable RTL Rules

⚡ Synthesizable Implementation Guidelines

Timing Contract: Clocked on posedge clk with active-low rst_n. Count increments on push, decrements on pop, holds on both.

Synthesis Constraints: Synthesizable Verilog-2001. No latch inference.

Architectural Deep Dive & Implementation Walkthrough

DMA Flow Control Using Watermarks

Direct Memory Access (DMA) controllers cannot wait until a buffer is completely full or completely empty before issuing bus requests. Doing so leads to buffer under-run or bus under-utilization.

Watermark Thresholds

  • Almost Full Watermark: Warns the DMA scatter-gather engine that the buffer is reaching capacity (e.g. 12/16 slots), allowing it to throttle upstream producers before overflow occurs.
  • Almost Empty Watermark: Signals that the buffer is nearly drained (e.g. 2/16 slots), prompting a burst read request to refill it before underflow occurs.

Common RTL Designer Pitfalls

⚠️ Common Mistakes to Avoid

Using a 4-bit counter for a depth-16 buffer, which wraps around from 15 to 0 instead of reaching 16.

Silicon & Hardware Engineering Notes

🛠️ ASIC vs FPGA Hardware Considerations

High-performance PCIe Root Complexes use programmable watermark thresholds to tune DMA burst lengths according to payload MTU.

Starter RTL Code

module top_module (
  input  wire       clk,
  input  wire       rst_n,
  input  wire       push,
  input  wire       pop,
  input  wire [3:0] almost_full_thresh,
  input  wire [3:0] almost_empty_thresh,
  output wire       almost_full,
  output wire       almost_empty,
  output wire       full,
  output wire       empty,
  output reg  [4:0] occupancy
);

  // Implement watermark evaluator:
  // 1. Capacity = 16 words.
  // 2. Track occupancy (0 to 16).
  // 3. full = (occupancy == 16); empty = (occupancy == 0).

Verified Reference Solution

🔒 Reveal Verified Reference RTL Solution
module top_module (
  input  wire       clk,
  input  wire       rst_n,
  input  wire       push,
  input  wire       pop,
  input  wire [3:0] almost_full_thresh,
  input  wire [3:0] almost_empty_thresh,
  output wire       almost_full,
  output wire       almost_empty,
  output wire       full,
  output wire       empty,
  output reg  [4:0] occupancy
);

  assign full  = (occupancy == 5'd16);
  assign empty = (occupancy == 5'd0);

  assign almost_full  = (occupancy >= {1'b0, almost_full_thresh});
  assign almost_empty = (occupancy <= {1'b0, almost_empty_thresh});

  wire valid_push = push && (!full || pop);
  wire valid_pop  = pop && !empty;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      occupancy <= 5'd0;
    end else begin
      case ({valid_push, valid_pop})
        2'b10: occupancy <= occupancy + 5'd1;
        2'b01: occupancy <= occupancy - 5'd1;
        default: ; // 2'b00 or 2'b11 -> maintain count
      endcase
    end
  end

endmodule

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Frequently Asked Questions

What does Programmable FIFO Watermark & Threshold Controller require?

Design a programmable watermark controller generating almost-full and almost-empty interrupt thresholds for DMA flow control. Implement it as Verilog module top_module matching the listed ports.

Is this design combinational or sequential?

Tags: advanced-rtl, fifo-and-buffer-architecture, systemverilog, asic, fpga. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.

How is my solution graded?

A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.

How does this challenge help with semiconductor interviews?

Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of Programmable FIFO Watermark & Threshold Controller to assess real-world synthesizability and race-condition awareness.