Glitch-Free Clock Mux — Clock Switching — RTL Design Practice & FSM Timing

Clocking & Timing · cdc, industry-rtl, arbiters, clock-domain-crossing, hard, clock-switching

Design a 2-to-1 glitch-free clock multiplexer that switches cleanly between asynchronous clocks clk0 and clk1 using dual feedback handshake registers.

RTL Problems / Level 4 · Clocking & Timing

What You Will Learn

By solving Glitch-Free Clock Mux — Clock Switching, you will acquire core industry skills:

Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design a 2-to-1 glitch-free clock multiplexer that switches cleanly between asynchronous clocks clk0 and clk1 using dual feedback handshake registers.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Objective: Understand clock gating hazards, runt pulse prevention, cross-coupled feedback disabling, and safe dynamic clock switching.

Prerequisites: Clock gating, negative-edge flip-flops, glitch analysis.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

Name	Dir	Width	Description
`clk0`	input	1	First input clock
`clk1`	input	1	Second input clock
`areset_n`	input	1	Asynchronous reset
`select`	input	1	Clock select (0 = clk0, 1 = clk1)
`clk_out`	output	1	Glitch-free output clock

Timing Constraints & Synthesizable RTL Rules

⚡ Synthesizable Implementation Guidelines

Timing Contract: When `select` changes, current clock is gated LOW at its falling edge before the new clock is enabled at its falling edge.

Synthesis Constraints: Never switch clocks with standard combinational MUXes! Output clock must never produce runt pulses or spikes.

Architectural Deep Dive & Implementation Walkthrough

Switching clocks is one of the most hazardous operations in digital hardware. A runt pulse (a clock pulse narrower than the minimum flip-flop pulse width $t_w$) can violate setup/hold times and trigger chip-wide functional collapse. The standard industry solution uses cross-coupled negative-edge flip-flops: the active clock is completely disabled while it is low, and only after confirmation of disablement is the second clock enabled while it is low.

Common RTL Designer Pitfalls

⚠️ Common Mistakes to Avoid

['Sampling on `posedge` instead of `negedge`: enabling a clock on its rising edge cuts into the clock phase, generating runt pulses.', 'Omitting the cross-coupling term `!q1_en` / `!q0_en`, allowing both clocks to be briefly enabled simultaneously.']

Silicon & Hardware Engineering Notes

🛠️ ASIC vs FPGA Hardware Considerations

This circuit is the exact standard cell architecture instantiated inside vendor clock multiplexer primitives (such as BUFGMUX on FPGAs or standard-cell CKLNQM cells in ASIC libraries).

Starter RTL Code

module top_module(
  input   clk0,
  input   clk1,
  input   areset_n,
  input   select,
  output  clk_out
);

  // 2-to-1 Glitch-Free Clock Multiplexer

endmodule

Verified Reference Solution

🔒 Reveal Verified Reference RTL Solution

module top_module(
  input   clk0,
  input   clk1,
  input   areset_n,
  input   select,
  output  clk_out
);
  reg q0_meta, q0_en;
  reg q1_meta, q1_en;

  // Clock 0 domain gating path (sampled on negedge clk0)
  always @(negedge clk0 or negedge areset_n) begin
    if (!areset_n) begin
      q0_meta <= 1'b0;
      q0_en   <= 1'b0;
    end else begin
      q0_meta <= (!select) && (!q1_en);
      q0_en   <= q0_meta;
    end
  end

  // Clock 1 domain gating path (sampled on negedge clk1)
  always @(negedge clk1 or negedge areset_n) begin
    if (!areset_n) begin
      q1_meta <= 1'b0;
      q1_en   <= 1'b0;
    end else begin
      q1_meta <= select && (!q0_en);
      q1_en   <= q1_meta;
    end
  end

  // Gated clock outputs OR'ed together
  assign clk_out = (clk0 & q0_en) | (clk1 & q1_en);
endmodule

Connected EcrioniX Learning Resources

Accelerate your VLSI engineering knowledge with these curated learning materials:

Dedicated Learning Roadmap

CDC, RDC and Low-Power RTL Roadmap →

Progress through step-by-step verified modules from fundamentals to advanced silicon design.

Knowledge Diagnostic

RTL Skill Assessment (10-30m) →

Benchmark your hardware knowledge across 10 semiconductor domains and receive study roadmaps.

In-Depth Theory Guide

Clock Domain Crossing & STA Mastery →

Explore foundational circuit theory, waveform timing, and physical hardware implementation.

Frequently Asked Questions

What does Glitch-Free Clock Mux — Clock Switching require?

Design a 2-to-1 glitch-free clock multiplexer that switches cleanly between asynchronous clocks clk0 and clk1 using dual feedback handshake registers. Implement it as Verilog module top_module matching the listed ports.

Is this design combinational or sequential?

Tags: cdc, industry-rtl, arbiters, clock-domain-crossing, hard, clock-switching. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.

How is my solution graded?

A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.

How does this challenge help with semiconductor interviews?

Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of Glitch-Free Clock Mux — Clock Switching to assess real-world synthesizability and race-condition awareness.