CDC, RDC and Low-Power RTL

Solve multi-clock domain challenges: 2-flop sync, pulse sync, multi-bit handshakes, glitch-free clock switching, and power sequencing.

Target Audience Senior RTL design engineers, synthesis engineers, and SoC integration specialists.

Prerequisites Sequential RTL Design (Path 3) and Static Timing Analysis (STA) basics.

Curriculum Goal Build reliable silicon-proven cross-domain hardware immune to metastability, runt pulses, and latch-up hazards.

Interactive Learning Roadmap

Module 1

⏱️ 45 mins

Metastability & Two-Flop Synchronizers

Calculate Mean Time Between Failures (MTBF) and safely synchronize slow-changing control signals.

Metastability physicsMTBF formula2-flop vs 3-flop syncData coherency

Practice RTL Problems (2)

○ Two-Flop Synchronizer — Single-Bit CDC hard 50 pts ○ 3-Flop CDC Synchronizer medium 25 pts

Module 2

⏱️ 60 mins

Pulse Synchronizers (Fast-to-Slow & Slow-to-Fast)

Transfer 1-cycle pulses across unrelated clock domains without losing pulses or causing false double-triggers.

Toggle flip-flop methodEdge-to-pulse detectionPulse stretching

Practice RTL Problems (3)

○ Pulse Synchronizer — Clock-Domain Crossing hard 50 pts ○ Toggle-Based Pulse Synchronizer Across Asynchronous Clock Domains Expert 50 pts ○ Stretch-and-Synchronize Pulse hard 50 pts

Module 3

⏱️ 65 mins

Multi-Bit Bus Handshake Synchronization

Safely transfer multi-bit data buses across clock domains using 4-phase REQ/ACK level handshakes.

Bus data skew hazardLevel-based 4-phase handshakeHold register data stability

Practice RTL Problems (2)

○ Multi-Bit Bus Handshake Clock-Domain Crossing (CDC) Expert 50 pts ○ CDC Bus Hold Register medium 25 pts

Module 4

⏱️ 50 mins

Reset Domain Crossing & Reset Synchronizers

Implement asynchronously asserted, synchronously deasserted reset bridges to prevent recovery time faults.

Reset recovery and removal timesAsync assertion, sync deassertionReset distribution trees

Practice RTL Problems (1)

○ Async-Assert / Sync-Deassert Reset hard 50 pts

Module 5

⏱️ 65 mins

Glitch-Free Clock Multiplexing

Switch dynamically between two asynchronous clocks without producing runt pulses.

Runt pulse hazardsNegative-edge flip-flop gatingMutual exclusion cross-feedback

Practice RTL Problems (2)

○ Glitch-Free Clock Mux — Clock Switching hard 50 pts ○ Glitch-Free Clock Multiplexer with Handshake Feedback Industry Challenge 50 pts

Module 6

⏱️ 45 mins

Integrated Clock Gating (ICG) Cells

Design latch-based integrated clock gating cells eliminating combinational glitching on clock lines.

Clock gating latch behaviorECLK = CLK & LATCH_ENPower format (UPF) mapping

Practice RTL Problems (1)

○ Integrated Clock Gating Cell (ICG) medium 25 pts

Module 7

⏱️ 55 mins

Programmable Clock Dividers

Generate integer, odd, and fractional clock division with 50% duty cycle.

Even divisionOdd division dual-edge recombinationClock tree jitter considerations

Practice RTL Problems (2)

○ Programmable Clock Divider hard 50 pts ○ Divide-by-3 Clock Pulse hard 50 pts

Module 8

⏱️ 55 mins

Async-FIFO Empty Flag Synchronization

Master pessimistic empty flag generation in the read clock domain.

Empty flag timingImmediate empty assertionSafe delayed empty deassertion

Practice RTL Problems (1)

○ Async-FIFO Empty Flag Synchronizer hard 50 pts

Module 9

⏱️ 55 mins

Async-FIFO Full Flag Synchronization

Master pessimistic full flag generation in the write clock domain.

Full flag timingImmediate full assertionSafe delayed full deassertion

Practice RTL Problems (1)

○ Async-FIFO Full Flag Synchronizer hard 50 pts

Module 10

⏱️ 70 mins

Multi-Rail SoC Power Sequencing Controllers

Implement deterministic power-up and power-down state machines with watchdog timeout protection.

IO -> Core -> PLL power rampReverse collapse orderCMOS latch-up preventionRail timeout watchdogs

Practice RTL Problems (2)

○ Power Rail Sequencer medium 25 pts ○ SoC Multi-Rail Power Sequencing Controller Industry Challenge 50 pts

Module 11

⏱️ 50 mins

Voltage Margin & Brownout Monitors

Implement digital voltage comparator monitors alerting PMUs of supply dips.

Brownout detectionVoltage droop thresholdsPower-management interrupts

Practice RTL Problems (2)

○ Voltage Margin Monitor easy 10 pts ○ Brown-Out Reset Detector medium 25 pts

Module 12

⏱️ 55 mins

Thermal Throttling & Power-Down FSMs

Protect high-density chips by triggering dynamic frequency scaling (DFS) under thermal stress.

Thermal trip pointsClock duty throttlingEmergency shutdown state machines

Practice RTL Problems (1)

○ Over-Temperature Throttle Monitor medium 25 pts

Why Master CDC, RDC and Low-Power RTL?

Build reliable silicon-proven cross-domain hardware immune to metastability, runt pulses, and latch-up hazards. Engineers who excel in this curriculum consistently outperform in technical interviews at semiconductor leaders such as NVIDIA, Qualcomm, Apple, and Intel because this roadmap focuses on synthesizability, edge-case assertions, and real simulation waveforms rather than purely theoretical textbook logic.

Recommended Learning Methodology

Step 1 — Understand the Concept: Read each module's core objectives and referenced EcrioniX guide.
Step 2 — Code the RTL: Open each practice challenge and implement top_module matching the exact ports and timing contract.
Step 3 — Inspect Waveforms: Run the remote cloud simulator to generate timing waveforms (VCD). Compare your signal transitions with the golden WaveDrom contract.
Step 4 — Review Explanations: Even after passing, review the editorial notes and hardware considerations to understand ASIC synthesis tradeoffs.

Frequently Asked Questions

What tools do I need for this roadmap?

None! All simulation testbenches run in the browser using our remote Icarus Verilog runner with automated waveform generation.

Are the reference solutions accessible?

Yes. Reference solutions are protected in an expandable solution drawer. We strongly encourage attempting and simulating your own RTL first.