Gray Code Sequence Checker

Verilog problems / Sequential Design

What you must build

Watch a stream of 4-bit values and flag whether each new sample really is a valid Gray-code step from the last one — exactly one bit changed, no more, no less.

Engineers use “Gray Code Sequence Checker” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  [3:0] code,
  output reg valid
);

  // Your code here — register the previous code; valid = exactly one bit differs from it (Hamming distance 1).

endmodule

Why this shows up in interviews

Gray Code Sequence Checker sits under Sequential Design (sequential, checker). Concept: The defining property of a Gray-code sequence is that consecutive values differ in exactly one bit. XOR the current sample against the registered previous one, then test whether that difference has exactly one bit set using the classic power-of-two trick: (diff != 0) && ((diff & (diff-1)) == 0) — a value with exactly one bit set becomes zero when ANDed with itself minus one. Replacing that check with a plain inequality ( code != prev ) only verifies that something changed, not that the change respects the one-bit-at-a-time rule — it would wave through a jump like 0110 to 0101 (two bits flipped) as if it were valid.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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