Hex 7-Segment Decoder

Verilog problems / Combinational Design

What you must build

Extend a BCD 7-segment decoder to the full hexadecimal range 0-F — the driver every FPGA dev-board hex display actually needs.

Engineers use “Hex 7-Segment Decoder” as a building block in combinational design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input      [3:0] hex,
  output reg [6:0] seg
);

  // Your code here — a case statement over all 16 hex values, 0-9 and A-F.

endmodule

Why this shows up in interviews

Hex 7-Segment Decoder sits under Combinational Design (combinational, display). Concept: This is the same seg[6:0]={a,b,c,d,e,f,g} active-high lookup table as a BCD decoder, just extended past 9: 0xA-0xF get their own standard segment patterns (A=1110111, b=0011111, C=1001110, d=0111101, E=1001111, F=1000111 — lowercase b/d because those digits render better with the segments available). A decoder that only implements case branches for 0-9 and lets A-F fall through to a default (usually blank) silently breaks the moment a real hex value above 9 reaches the display.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• 2-to-1 Multiplexer — Select between two 1-bit inputs using sel. When sel=0 output a; when sel=1 output b.
• 1-Bit Full Adder — Compute sum and carry-out for a + b + cin.
• 4-to-1 Multiplexer — Select one of four 1-bit inputs using a 2-bit sel. sel=00→in0, 01→in1, 10→in2, 11→in3.
• 4-to-2 Priority Encoder — Output the index of the highest-priority (MSB-most) set bit in a 4-bit input, plus a valid flag when any bit is set.

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