Lockstep Dual-Core Comparator

Verilog problems / Sequential Design

What you must build

The functional-safety watchdog behind lockstep processors: compare two redundant cores' outputs every cycle, and once they ever disagree, latch that fault permanently.

Engineers use “Lockstep Dual-Core Comparator” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  valid_a,
  input  [7:0] data_a,
  input  valid_b,
  input  [7:0] data_b,
  output reg fault
);

  // Your code here — when both valid and data_a != data_b, latch fault=1. Never clear it except on rst.

Why this shows up in interviews

Lockstep Dual-Core Comparator sits under Sequential Design (sequential, safety). Concept: In a safety-critical lockstep design (the kind ISO 26262 automotive silicon relies on), a fault flag must be sticky — once a mismatch between the two redundant cores is observed, the fault must stay asserted until an explicit reset, never silently clearing itself just because a later comparison happens to match again: if(mismatch) fault<=1; (no path that ever sets it back to 0 except reset). Writing fault <= mismatch instead looks almost identical but re-evaluates the fault fresh every cycle, so a single transient glitch gets silently forgotten the moment the next comparison is clean — exactly the failure mode a lockstep safety mechanism exists to catch.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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