Magic 8-Ball Fortune Teller

Verilog problems / Fun & Games

What you must build

Give a "random-feeling" fortune-teller answer on every shake using a self-advancing 3-bit LFSR — a tiny, deterministic taste of pseudo-randomness in hardware.

Engineers use “Magic 8-Ball Fortune Teller” as a building block in fun & games. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  shake,
  output [2:0] answer
);

  // Your code here — 3-bit LFSR, feedback = lfsr[2]^lfsr[0], seed on reset = 3'b001, advances on shake.

endmodule

Why this shows up in interviews

Magic 8-Ball Fortune Teller sits under Fun & Games (sequential, lfsr). Concept: A 3-bit Fibonacci LFSR with feedback tap q[2]^q[0] cycles through all 7 nonzero 3-bit states before repeating, giving a fixed but non-obvious-looking sequence of "answers" each time shake pulses: lfsr <= {lfsr[1:0], lfsr[2]^lfsr[0]}; . The tap position matters — a 3-bit LFSR has exactly two maximal-length taps ( q2^q1 and q2^q0 ), and swapping one for the other still produces a valid-looking cycling pattern, just a completely different (and here, wrong) sequence of answers.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

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