RTL Problems / Level 3 · Memory Architectures
What You Will Learn
By solving Single-Port RAM with Write Enable — Memory Control, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Implement a 32-word x 8-bit single-port synchronous RAM with read-first (read-during-write) behavior.
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
Prerequisites: Synchronous RAM, write enable gating.
Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Name | Dir | Width | Description |
|---|---|---|---|
clk | input | 1 | Clock signal |
we | input | 1 | Write enable |
addr | input | 5 | 5-bit word address (0 to 31) |
din | input | 8 | 8-bit input data to write |
dout | output | 8 | 8-bit read data output |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: When we=1 at posedge clk, old memory contents are presented on dout (read-first), while din is written into memory.
Synthesis Constraints: Single-port architecture: read and write share the same clock and address bus.
Architectural Deep Dive & Implementation Walkthrough
Common RTL Designer Pitfalls
['Assigning `dout <= din` during writes, turning it into write-first mode instead of read-first mode.', 'Using blocking assignments, which breaks delta-cycle read-first ordering in simulation.']
Silicon & Hardware Engineering Notes
Selecting read-first mode in BRAM saves power and avoids bypass multiplexer logic in FPGA routing fabrics.
Starter RTL Code
module top_module(
input clk,
input we,
input [4:0] addr,
input [7:0] din,
output reg [7:0] dout
);
// 32x8 single-port RAM with read-first semantics
endmodule
Verified Reference Solution
🔒 Reveal Verified Reference RTL Solution
module top_module(
input clk,
input we,
input [4:0] addr,
input [7:0] din,
output reg [7:0] dout
);
reg [7:0] ram [0:31];
always @(posedge clk) begin
dout <= ram[addr]; // read-first: sample prior memory content
if (we)
ram[addr] <= din;
end
endmodule
Related RTL Problems in Level 3
- Synchronous RAM — Memory Read/Write — Design a 16-word by 8-bit synchronous RAM (16x8) with synchronous write and synchronous read.
- Synchronous FIFO — FIFO Architecture — Design an 8-entry by 8-bit synchronous First-In First-Out (FIFO) buffer with write enable (wr_en), read enable (rd_en), full, and empty flags.
- FIFO Full and Empty Detection — Pointer Logic — Generate full and empty flags for an 8-entry circular FIFO using 4-bit pointers (3-bit address + 1 MSB wrap bit) without an occupancy counter.
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Frequently Asked Questions
What does Single-Port RAM with Write Enable — Memory Control require?
Implement a 32-word x 8-bit single-port synchronous RAM with read-first (read-during-write) behavior. Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: memory, fifo, protocols, apb, uart, hard, sram-blocks. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of Single-Port RAM with Write Enable — Memory Control to assess real-world synthesizability and race-condition awareness.