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Part of Curriculum: Memory and FIFO Design (Module 1: Synchronous RAM Inference & Memory Arrays)
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Level 3 Hard ★ Flagship #23 50 pts ✓ Solved

Synchronous RAM — Memory Read/Write

Memory Architectures · memory, fifo, protocols, apb, uart, hard, sram-blocks

Design a 16-word by 8-bit synchronous RAM (16x8) with synchronous write and synchronous read.

Module Specification
Write a synthesizable Verilog module named top_module matching the ports below exactly.
📐 Circuit Schematic Diagram
weaddr[3:0]data[7:0]q[7:0]>clkSYNCHRONOUS RAMRAM / STORAGE ARRAY
⚡ Timing & Synthesizability Constraints

Timing Contract: Write occurs on `posedge clk` when `we=1`. Read data `q` updates on `posedge clk` from address `addr` (1-cycle read latency).

RTL Constraints: Synthesizable memory array: `reg [7:0] ram [0:15];`. Read output must be registered.

Objective: Understand inferring block RAMs in synthesizable Verilog, multidimensional arrays, and synchronous address register pipelines.

Prerequisites: Sequential logic, arrays, memory read/write cycles.
Port Contract
NameDirWidthDescription
clkinput1Master memory clock
weinput1Write enable (1 = write, 0 = read)
addrinput44-bit word address (0 to 15)
datainput88-bit write data input
qoutput88-bit registered read data output
Expected Waveform (Golden Timing Contract)
💡 Need Guidance? Progressive Hints (3 Levels)
Hint 1: Conceptual Direction & Hardware Primitives
Declare a memory array: `reg [7:0] ram [0:15];`.
Hint 2: Implementation Architecture & Approach
Inside `always @(posedge clk)`: write when `we` is asserted: `if (we) ram[addr] <= data;`.
Hint 3: Edge Cases, Timing & Verilog Syntax
Read synchronously into `q`: `q <= ram[addr];`.
🔒 Reveal Verified Reference RTL Solution (Click to expand)
⚠️ Self-Discovery Warning: Try solving and simulating first! Viewing the verified reference implementation will bypass the real debugging experience.
Verified Synthesizable RTL 
module top_module(
  input        clk,
  input        we,
  input  [3:0] addr,
  input  [7:0] data,
  output reg [7:0] q
);
  reg [7:0] ram [0:15];

  always @(posedge clk) begin
    if (we)
      ram[addr] <= data;
    q <= ram[addr];
  end
endmodule
Verilog-2001 / SV Saved
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Simulation Timing Diagram (VCD Waveform)
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RTL Problems / Level 3 · Memory Architectures

What You Will Learn

By solving Synchronous RAM — Memory Read/Write, you will acquire core industry skills:

  • Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
  • Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
  • Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
  • Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design a 16-word by 8-bit synchronous RAM (16x8) with synchronous write and synchronous read.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Objective: Understand inferring block RAMs in synthesizable Verilog, multidimensional arrays, and synchronous address register pipelines.

Prerequisites: Sequential logic, arrays, memory read/write cycles.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

NameDirWidthDescription
clkinput1Master memory clock
weinput1Write enable (1 = write, 0 = read)
addrinput44-bit word address (0 to 15)
datainput88-bit write data input
qoutput88-bit registered read data output

Timing Constraints & Synthesizable RTL Rules

⚡ Synthesizable Implementation Guidelines

Timing Contract: Write occurs on `posedge clk` when `we=1`. Read data `q` updates on `posedge clk` from address `addr` (1-cycle read latency).

Synthesis Constraints: Synthesizable memory array: `reg [7:0] ram [0:15];`. Read output must be registered.

Architectural Deep Dive & Implementation Walkthrough

Modern FPGA and ASIC block memories (BRAM / SRAM macros) operate synchronously: addresses and write enables are sampled at the clock edge, and data appears at the output after the clock-to-out access time ($t_{co}$). Registering the read address or output enables mapping directly into embedded hardware Block RAM primitives rather than distributed LUT RAM.

Common RTL Designer Pitfalls

⚠️ Common Mistakes to Avoid

['Writing asynchronous read logic (`assign q = ram[addr];`). In modern FPGAs, large memories cannot be read asynchronously without forcing the tool to synthesize millions of LUTs.', 'Confusing array dimensions: `reg [7:0] ram [0:15]` is 16 words of 8-bit width (not `reg [15:0] ram [0:7]`).']

Silicon & Hardware Engineering Notes

🛠️ ASIC vs FPGA Hardware Considerations

In FPGA synthesis (Xilinx Vivado, Intel Quartus), this exact coding template automatically infers dedicated Block RAM (BRAM) tiles without consuming any logic slices.

Starter RTL Code

module top_module(
  input        clk,
  input        we,
  input  [3:0] addr,
  input  [7:0] data,
  output reg [7:0] q
);

  // 16x8 Synchronous RAM with registered read output

endmodule

Verified Reference Solution

🔒 Reveal Verified Reference RTL Solution
module top_module(
  input        clk,
  input        we,
  input  [3:0] addr,
  input  [7:0] data,
  output reg [7:0] q
);
  reg [7:0] ram [0:15];

  always @(posedge clk) begin
    if (we)
      ram[addr] <= data;
    q <= ram[addr];
  end
endmodule

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Frequently Asked Questions

What does Synchronous RAM — Memory Read/Write require?

Design a 16-word by 8-bit synchronous RAM (16x8) with synchronous write and synchronous read. Implement it as Verilog module top_module matching the listed ports.

Is this design combinational or sequential?

Tags: memory, fifo, protocols, apb, uart, hard, sram-blocks. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.

How is my solution graded?

A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.

How does this challenge help with semiconductor interviews?

Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of Synchronous RAM — Memory Read/Write to assess real-world synthesizability and race-condition awareness.