RTL Problems / Level 2 · Finite State Machines
What You Will Learn
By solving Mealy Sequence Detector — FSM Output Behavior, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Design a Mealy finite state machine detecting sequence `101`. Unlike a Moore FSM, output `detected` asserts immediately in the same cycle when the final bit arrives.
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
Prerequisites: Moore FSM, combinational path analysis.
Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Name | Dir | Width | Description |
|---|---|---|---|
clk | input | 1 | Clock signal |
areset_n | input | 1 | Active-low asynchronous reset |
din | input | 1 | Bitstream input |
detected | output | 1 | High when sequence 101 completes |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: Output `detected` asserts combinational with `din` during state S2 when `din=1`.
Synthesis Constraints: Overlapping sequence support (`10101` produces 2 detections).
Architectural Deep Dive & Implementation Walkthrough
Common RTL Designer Pitfalls
['Registering the output in a Moore-style block, which introduces a 1-cycle delay.', 'Forgetting to verify overlap transitions from S2.']
Silicon & Hardware Engineering Notes
Mealy outputs create combinational paths spanning between clock domains or modules, complicating timing closure. In high-speed ASIC designs, Moore outputs or registered Mealy outputs (Medvedev FSMs) are preferred.
Starter RTL Code
module top_module(
input clk,
input areset_n,
input din,
output detected
);
// Mealy FSM detecting sequence 101
endmodule
Verified Reference Solution
🔒 Reveal Verified Reference RTL Solution
module top_module(
input clk,
input areset_n,
input din,
output detected
);
localparam S0 = 2'd0; // Idle
localparam S1 = 2'd1; // '1'
localparam S2 = 2'd2; // '10'
reg [1:0] state, next_state;
always @(posedge clk or negedge areset_n) begin
if (!areset_n)
state <= S0;
else
state <= next_state;
end
always @(*) begin
case (state)
S0: next_state = din ? S1 : S0;
S1: next_state = din ? S1 : S2;
S2: next_state = din ? S1 : S0;
default: next_state = S0;
endcase
end
// Mealy output: asserts during S2 when din=1
assign detected = (state == S2) && (din == 1'b1);
endmodule
Related RTL Problems in Level 2
- D Flip-Flop — Positive-Edge-Triggered Storage — Implement a basic 1-bit positive-edge-triggered D flip-flop without reset.
- D Flip-Flop with Asynchronous Reset — Reset Behavior — Design a D flip-flop with active-low asynchronous reset (areset_n). Reset forces q to 0 immediately, independent of clk.
- D Flip-Flop with Synchronous Reset — Clocked Reset — Implement a D flip-flop with active-high synchronous reset (sync_rst). The reset takes effect only on the rising clock edge.
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Frequently Asked Questions
What does Mealy Sequence Detector — FSM Output Behavior require?
Design a Mealy finite state machine detecting sequence `101`. Unlike a Moore FSM, output `detected` asserts immediately in the same cycle when the final bit arrives. Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: sequential, fsm, counters, medium, mealy-fsm. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of Mealy Sequence Detector — FSM Output Behavior to assess real-world synthesizability and race-condition awareness.