RTL Problems / Level 2 · Finite State Machines
What You Will Learn
By solving Moore Sequence Detector — FSM Design, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Design a Moore finite state machine that detects overlapping sequence `1011` on serial input `din`. Output `detected` is 1 when in the match state.
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
Prerequisites: State transition diagrams, FSM state variables, parameter/localparam enums.
Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Name | Dir | Width | Description |
|---|---|---|---|
clk | input | 1 | Clock signal |
areset_n | input | 1 | Active-low asynchronous reset |
din | input | 1 | Serial bitstream input |
detected | output | 1 | High when sequence 1011 is detected |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: In a Moore machine, output depends strictly on current state, appearing 1 cycle after the final input bit.
Synthesis Constraints: Overlapping sequences must be detected (e.g. `1011011` asserts detected twice).
Architectural Deep Dive & Implementation Walkthrough
Common RTL Designer Pitfalls
['Resetting to S0 after detection instead of S1 (if din=1) or S2 (if din=0), breaking overlap support.', 'Creating latches by missing cases in `always @(*)`.']
Silicon & Hardware Engineering Notes
Because Moore outputs depend only on state flip-flops, they are glitch-free and have clean clock-to-output timing. However, they respond one cycle later than Mealy machines.
Starter RTL Code
module top_module(
input clk,
input areset_n,
input din,
output detected
);
// Moore FSM detecting overlapping 1011
endmodule
Verified Reference Solution
🔒 Reveal Verified Reference RTL Solution
module top_module(
input clk,
input areset_n,
input din,
output detected
);
localparam S0 = 3'd0; // Idle / none
localparam S1 = 3'd1; // '1'
localparam S2 = 3'd2; // '10'
localparam S3 = 3'd3; // '101'
localparam S4 = 3'd4; // '1011' (Match)
reg [2:0] state, next_state;
always @(posedge clk or negedge areset_n) begin
if (!areset_n)
state <= S0;
else
state <= next_state;
end
always @(*) begin
case (state)
S0: next_state = din ? S1 : S0;
S1: next_state = din ? S1 : S2;
S2: next_state = din ? S3 : S0;
S3: next_state = din ? S4 : S2;
S4: next_state = din ? S1 : S2;
default: next_state = S0;
endcase
end
assign detected = (state == S4);
endmodule
Related RTL Problems in Level 2
- D Flip-Flop — Positive-Edge-Triggered Storage — Implement a basic 1-bit positive-edge-triggered D flip-flop without reset.
- D Flip-Flop with Asynchronous Reset — Reset Behavior — Design a D flip-flop with active-low asynchronous reset (areset_n). Reset forces q to 0 immediately, independent of clk.
- D Flip-Flop with Synchronous Reset — Clocked Reset — Implement a D flip-flop with active-high synchronous reset (sync_rst). The reset takes effect only on the rising clock edge.
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Frequently Asked Questions
What does Moore Sequence Detector — FSM Design require?
Design a Moore finite state machine that detects overlapping sequence `1011` on serial input `din`. Output `detected` is 1 when in the match state. Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: sequential, fsm, counters, medium, moore-fsm. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of Moore Sequence Detector — FSM Design to assess real-world synthesizability and race-condition awareness.