Parameterized Synchronous FIFO with Simultaneous Read/Write

RTL Problems / Level 8 · Advanced RTL & Protocol Design

What You Will Learn

By solving Parameterized Synchronous FIFO with Simultaneous Read/Write, you will acquire core industry skills:

• Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
• Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
• Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
• Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design a parameterized synchronous FIFO supporting simultaneous read and write operations without underflow or overflow hazards.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

Timing Constraints & Synthesizable RTL Rules

Architectural Deep Dive & Implementation Walkthrough

Common RTL Designer Pitfalls

Silicon & Hardware Engineering Notes

Starter RTL Code

module top_module #(
  parameter DATA_WIDTH = 32,
  parameter DEPTH      = 8
)(
  input  wire                  clk,
  input  wire                  rst_n,
  input  wire                  wr_en,
  input  wire [DATA_WIDTH-1:0] wr_data,
  input  wire                  rd_en,
  output reg  [DATA_WIDTH-1:0] rd_data,
  output wire                  full,
  output wire                  empty,
  output reg  [3:0]            count
);

  // Implement parameterized synchronous FIFO:
  // 1. circular write and read pointers.
  // 2. count tracks number of valid items in FIFO (0 to DEPTH).

Verified Reference Solution

module top_module #(
  parameter DATA_WIDTH = 32,
  parameter DEPTH      = 8
)(
  input  wire                  clk,
  input  wire                  rst_n,
  input  wire                  wr_en,
  input  wire [DATA_WIDTH-1:0] wr_data,
  input  wire                  rd_en,
  output reg  [DATA_WIDTH-1:0] rd_data,
  output wire                  full,
  output wire                  empty,
  output reg  [3:0]            count
);

  reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
  reg [2:0] wr_ptr, rd_ptr;

  assign full  = (count == DEPTH);
  assign empty = (count == 4'd0);

  wire valid_wr = wr_en && (!full || rd_en);
  wire valid_rd = rd_en && !empty;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      wr_ptr  <= 3'd0;
      rd_ptr  <= 3'd0;
      count   <= 4'd0;
      rd_data <= {DATA_WIDTH{1'b0}};
    end else begin
      if (valid_wr) begin
        mem[wr_ptr] <= wr_data;
        wr_ptr      <= (wr_ptr + 3'd1) % DEPTH;
      end

      if (valid_rd) begin
        rd_data <= mem[rd_ptr];
        rd_ptr  <= (rd_ptr + 3'd1) % DEPTH;
      end

      case ({valid_wr, valid_rd})
        2'b10: count <= count + 4'd1;
        2'b01: count <= count - 4'd1;
        default: ; // 2'b00 or 2'b11 -> hold count
      endcase
    end
  end

endmodule

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Frequently Asked Questions