Parking Garage Spot Counter

Verilog problems / Fun & Games

What you must build

Track available spots in an 8-space garage as cars enter and exit, refusing to go negative when it's already full — an up/down counter with real-world guard rails.

Engineers use “Parking Garage Spot Counter” as a building block in fun & games. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  car_in,
  input  car_out,
  output reg [3:0] available,
  output full
);

  // Your code here — capacity is 8. car_in decrements available (never below 0),
  // car_out increments it (never above 8). full = (available==0).

Why this shows up in interviews

Parking Garage Spot Counter sits under Fun & Games (sequential, counter). Concept: Available spots decrement on car_in and increment on car_out , but only when it's safe to do so: never decrement below 0, never increment past capacity. The full flag is simply available==0 . Forgetting the available!=0 guard on the decrement path means a car_in pulse that arrives while the garage is already full silently underflows the counter to 15 (since it's unsigned) instead of holding at 0 — the garage would appear to gain fifteen phantom free spots the instant it should have stayed completely full.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

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