Parking Meter Timer

Verilog problems / Fun & Games

What you must build

A coin-fed countdown timer that flags a violation the instant time runs out and no more coins arrive — a real-world countdown-with-guard pattern.

Engineers use “Parking Meter Timer” as a building block in fun & games. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  tick,
  input  coin,
  output reg [7:0] time_remaining,
  output reg violation
);

  // Your code here — coin: time_remaining += 10, violation <= 0.
  // tick (no coin): if time_remaining > 0, decrement it; else set violation. Never let it underflow.

Why this shows up in interviews

Parking Meter Timer sits under Fun &amp; Games (sequential, counter, fsm). Concept: Each coin adds time and clears any violation; each tick spends one unit of time, but only while there's time left to spend: if(time_remaining>0) time_remaining<=time_remaining-1; else violation<=1; . Dropping that guard — decrementing unconditionally on every tick regardless of whether time is already at 0 — lets the counter underflow past zero and wrap around to its maximum value (255) the instant it should have simply stayed at 0 flagging a violation, the same countdown-underflow bug that shows up anywhere a counter is allowed to keep counting down past its floor.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• Simon Says Sequence Checker — Check a player's button presses against a fixed 4-step target sequence, one press at a time — freeze on the first mistake, celebrate after the last correct press.
• Top-3 Leaderboard Tracker — Maintain the 3 highest scores seen so far in sorted order as new scores stream in — an insertion-sort shift register in miniature.
• Leap Year Checker — Determine whether a given year is a leap year — the classic "divisible by 4, except by 100, except-except by 400" rule as combinational logic.
• FizzBuzz Encoder — The classic programming-interview puzzle, recast as combinational hardware: classify a number as Fizz, Buzz, FizzBuzz, or itself.

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