Combination Safe with Lockout

Verilog problems / Sequential Design

What you must build

A combination lock that locks itself out entirely after 3 failed attempts — a security-flavored extension of the basic combination lock FSM.

Engineers use “Combination Safe with Lockout” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  [1:0] code,
  output unlocked,
  output locked_out
);

  // Your code here — combination-lock FSM (2,1,3) plus a fail counter that locks out after 3 failures.

endmodule

Why this shows up in interviews

Combination Safe with Lockout sits under Sequential Design (sequential, fsm). Concept: Layer a failure counter on top of the combination-lock FSM: every time a wrong digit knocks progress back to the start (from partway through the sequence), increment fails . On the 3rd such failure, latch a permanent locked flag that gates the entire state machine — once set, no further digit has any effect until reset.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

FAQ