Sequence Detector: 1011 (Overlapping)

Verilog problems / Sequential Design

What you must build

A Moore FSM that watches a serial bit stream and pulses high for one cycle right after it spots the pattern 1011 — overlapping matches count.

Engineers use “Sequence Detector: 1011 (Overlapping)” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  in,
  output detected
);

  // Your code here — a 5-state FSM (S0..S4) tracking match progress works well.

endmodule

Why this shows up in interviews

Sequence Detector: 1011 (Overlapping) sits under Sequential Design (sequential, fsm). Concept: Track "longest prefix of 1011 matched so far" as a 5-state machine (S0..S4). Overlap matters: after matching 1011, the last bit of that match can also start the next one, so S4 doesn't reset all the way back to S0 — it re-enters the automaton the same way S1 would. detected is a Moore output: it is simply (state == S4) , true for one full cycle after the fourth matching bit is clocked in.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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