RTL Problems / Level 2 · Sequential Logic
What You Will Learn
By solving 4-Bit Shift Register — Data Shifting, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Implement a 4-bit serial-in parallel-out (SIPO) shift register. On each clock edge, data shifts left: q[3]<=q[2], q[2]<=q[1], q[1]<=q[0], q[0]<=din.
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
Prerequisites: Flip-flop cascades, bit concatenation syntax.
Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Name | Dir | Width | Description |
|---|---|---|---|
clk | input | 1 | Master clock |
areset_n | input | 1 | Active-low asynchronous reset |
din | input | 1 | Serial data input |
q | output | 4 | 4-bit parallel register output |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: Data shifts by one position on each `posedge clk`. Requires 4 clock cycles to fully load 4 serial bits.
Synthesis Constraints: Non-blocking assignments to model pipeline flop stages accurately.
Architectural Deep Dive & Implementation Walkthrough
Common RTL Designer Pitfalls
['Using blocking assignments (`=`), causing all flip-flops to update in sequence in a single simulation delta cycle, corrupting the pipeline.', 'Shifting in the wrong direction (confusing `{din, q[3:1]}` right shift with `{q[2:0], din}` left shift).']
Silicon & Hardware Engineering Notes
Modern FPGAs (AMD/Xilinx) can configure a single LUT as a 32-bit shift register (SRL32), implementing deep shift registers with zero flip-flop overhead.
Starter RTL Code
module top_module(
input clk,
input areset_n,
input din,
output reg [3:0] q
);
// 4-bit left shift register
endmodule
Verified Reference Solution
🔒 Reveal Verified Reference RTL Solution
module top_module(
input clk,
input areset_n,
input din,
output reg [3:0] q
);
always @(posedge clk or negedge areset_n) begin
if (!areset_n)
q <= 4'b0000;
else
q <= {q[2:0], din};
end
endmodule
Related RTL Problems in Level 2
- D Flip-Flop — Positive-Edge-Triggered Storage — Implement a basic 1-bit positive-edge-triggered D flip-flop without reset.
- D Flip-Flop with Asynchronous Reset — Reset Behavior — Design a D flip-flop with active-low asynchronous reset (areset_n). Reset forces q to 0 immediately, independent of clk.
- D Flip-Flop with Synchronous Reset — Clocked Reset — Implement a D flip-flop with active-high synchronous reset (sync_rst). The reset takes effect only on the rising clock edge.
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Frequently Asked Questions
What does 4-Bit Shift Register — Data Shifting require?
Implement a 4-bit serial-in parallel-out (SIPO) shift register. On each clock edge, data shifts left: q[3]<=q[2], q[2]<=q[1], q[1]<=q[0], q[0]<=din. Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: sequential, fsm, counters, medium, shift-registers. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of 4-Bit Shift Register — Data Shifting to assess real-world synthesizability and race-condition awareness.