Simon Says Sequence Checker

Verilog problems / Fun & Games

What you must build

Check a player's button presses against a fixed 4-step target sequence, one press at a time — freeze on the first mistake, celebrate after the last correct press.

Engineers use “Simon Says Sequence Checker” as a building block in fun & games. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  [1:0] press,
  input  press_valid,
  output reg [1:0] step,
  output reg fail,
  output reg success
);

  // Your code here — fixed target sequence [1,3,0,2]. On press_valid (while !fail && !success):
  // if press matches target[step], advance step (or set success at step 3); else set fail and freeze.

Why this shows up in interviews

Simon Says Sequence Checker sits under Fun & Games (sequential, fsm, game-logic). Concept: The checker advances one step for every press that matches the target sequence, and the moment a press is wrong it must latch failure and stop reacting to anything else until reset: else if(!fail && !success && press_valid) ... . Dropping the !fail half of that guard is a subtle "the game doesn't actually end" bug — the fail flag still gets set correctly on the first wrong press, but because the FSM keeps evaluating later presses against the still-unfrozen step , a lucky continuation can silently advance the sequence (or even reach success) after the player already lost.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• Parking Meter Timer — A coin-fed countdown timer that flags a violation the instant time runs out and no more coins arrive — a real-world countdown-with-guard pattern.
• Top-3 Leaderboard Tracker — Maintain the 3 highest scores seen so far in sorted order as new scores stream in — an insertion-sort shift register in miniature.
• Leap Year Checker — Determine whether a given year is a leap year — the classic "divisible by 4, except by 100, except-except by 400" rule as combinational logic.
• FizzBuzz Encoder — The classic programming-interview puzzle, recast as combinational hardware: classify a number as Fizz, Buzz, FizzBuzz, or itself.

FAQ