Valid/Ready Skid Buffer

Verilog problems / Sequential Design

What you must build

Absorb one cycle of downstream backpressure without dropping data — the 1-entry buffer that makes a ready/valid handshake safe to pipeline.

Engineers use “Valid/Ready Skid Buffer” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  valid_in,
  output ready_out,
  input  [7:0] data_in,
  output reg valid_out,
  input  ready_in,
  output reg [7:0] data_out
);

  // Your code here — 1-entry skid buffer: catch one cycle of new data when downstream stalls, ready_out=0 while it's occupied.

Why this shows up in interviews

Valid/Ready Skid Buffer sits under Sequential Design (sequential, protocol, datapath). Concept: When downstream stalls ( ready_in low) but upstream still has new data waiting, that data has nowhere to go — unless a skid buffer catches it: if(valid_out && valid_in) begin skid_data<=data_in; skid_valid<=1; end , and ready_out drops to stop upstream from sending more until the skid slot drains. Wiring ready_out straight through to ready_in (skipping the skid logic entirely) looks like a handshake but has no buffering at all — the moment downstream stalls for even one cycle, whatever data arrives that cycle is simply lost, since nothing is holding it.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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