Thermostat with Hysteresis

Verilog problems / Sequential Design

What you must build

Control a heater with a dead-band between the on and off thresholds, so it doesn't chatter on and off every time the temperature crosses a single setpoint.

Engineers use “Thermostat with Hysteresis” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  [7:0] temp,
  output reg heater_on
);

  // Your code here — turn on at temp<=68, turn off at temp>=72, hold state in the deadband (69-71).

endmodule

Why this shows up in interviews

Thermostat with Hysteresis sits under Sequential Design (sequential, fsm). Concept: A single-threshold thermostat oscillates rapidly whenever the temperature hovers right at the setpoint — every tiny fluctuation flips the heater. Hysteresis fixes this with two thresholds: turn on at or below a LOW point, turn off at or above a HIGH point, and hold the current state anywhere in between: if(temp<=LOW) on<=1; else if(temp>=HIGH) on<=0; (no else — the deadband case falls through and keeps the old value). Collapsing this to one threshold ( on <= temp<70 ) throws away the memory that makes hysteresis work, so the heater flips state on every single sample near 70 instead of holding steady.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

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• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
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