Two-Way Traffic Intersection

Verilog problems / Sequential Design

What you must build

Control two perpendicular traffic lights so that only one direction is ever green or yellow at a time — a safety-critical mutual-exclusion FSM.

Engineers use “Two-Way Traffic Intersection” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  output [1:0] ns_light,
  output [1:0] ew_light
);

  // Your code here — NS green(3) -> NS yellow(2) -> EW green(3) -> EW yellow(2) -> repeat. Never both green.

endmodule

Why this shows up in interviews

Two-Way Traffic Intersection sits under Sequential Design (sequential, fsm). Concept: A 4-state cycle — NS green (3 cycles), NS yellow (2 cycles), EW green (3 cycles), EW yellow (2 cycles) — guarantees the two directions never overlap, because each direction's light is driven purely from the current state: ns_light is only ever non-red during NSG / NSY , and ew_light only during EWG / EWY . Letting both outputs derive green from overlapping state conditions (even briefly, like during a shared reset state) creates a real collision hazard.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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