DDR & LPDDR — Memory Explained
The RAM inside every computer, phone, and server — from what "double data rate" really means to DDR5 sub-channels, LPDDR5 power tricks, and how timing parameters like CL-tRCD-tRP work.
1. What is DDR Memory?
DDR SDRAM (Double Data Rate Synchronous Dynamic RAM) is the main memory technology used in virtually every computer, phone, server, and embedded system today. Breaking the name down:
- Dynamic — each bit is stored as a tiny charge in a capacitor that leaks over time. The memory controller must periodically refresh (recharge) every row, or data is lost.
- Synchronous — all operations are synchronized to a clock signal from the memory controller.
- Double Data Rate — data is transferred on both the rising edge and the falling edge of the clock. A 1600 MHz clock gives 3200 MT/s (mega-transfers per second) — hence DDR4-3200 running at 1600 MHz.
SDR SDRAM = 1 transfer per clock cycle. DDR SDRAM = 2 transfers per clock cycle (one on each edge). Same clock frequency → 2× the data rate.
Fig 1 — SDR transfers once per clock; DDR transfers on both edges → 2× data rate at the same frequency
2. DDR Generations — Speed & Specs
Each DDR generation roughly doubles bandwidth while reducing voltage. The speed rating (e.g., DDR4-3200) is in MT/s — mega-transfers per second — which equals twice the clock frequency.
| Gen | Year | Voltage | Prefetch | Speed (MT/s) | Key addition |
|---|---|---|---|---|---|
| DDR1 | 2000 | 2.5 V | 2n | 200 – 400 | First DDR standard; replaced SDR SDRAM |
| DDR2 | 2003 | 1.8 V | 4n | 400 – 1066 | 4n prefetch, ODT (On-Die Termination) |
| DDR3 | 2007 | 1.5 V | 8n | 800 – 2133 | 8n prefetch, ZQ calibration, Fly-by topology |
| DDR4 | 2014 | 1.2 V | 8n | 1600 – 3200 | Bank Groups, CRC data integrity, CA parity, higher density |
| DDR5 | 2020 | 1.1 V | 16n | 4800 – 8400 | 2 sub-channels / DIMM, on-die ECC, PMIC on DIMM, Decision Feedback Equalization |
DRAM internally reads multiple bits per access cycle to keep the high-speed data bus busy. DDR4's 8n prefetch means each DRAM array access reads 8× the bus width internally — 8 × 64 bits = 512 bits per access — then streams them out at full DDR speed. DDR5 increases this to 16n.
3. Memory Hierarchy
DDR memory is organized in a strict hierarchy from the system level down to individual storage cells. Understanding this hierarchy is essential for both chip design and performance optimization.
Fig 2 — DDR memory hierarchy: Channel → DIMM → Rank → DRAM Chip → Bank Group → Bank → Row → Column
Key hierarchy concepts
- Channel — independent 64-bit data bus (+ clock, address, command) from the memory controller. More channels = more total bandwidth.
- DIMM — physical module plugged into a slot. Contains all DRAM chips for one or two ranks.
- Rank — a set of DRAM chips (typically 8 chips × 8 bits = 64 bits) that are chip-selected and accessed together as one 64-bit wide word.
- Bank Group — introduced in DDR4. Groups of 4 banks that can be accessed back-to-back with reduced timing penalties, enabling pipelining between groups.
- Bank — an independent 2D array (rows × columns) inside each DRAM chip. A bank has one active row (sense amplifier latch) at a time.
- Row (Page) — one row of the DRAM array, activated by an ACTIVATE command. Once open, columns within it can be read/written without penalty.
- Column — the specific address within the active row to read or write.
4. Timing Parameters — CL, tRCD, tRP, tRAS
DDR memory sticks are labelled with four numbers, e.g., 16-18-18-38 (DDR4-3200) or 32-38-38-76 (DDR5-4800). These are clock-cycle counts for the four primary timing parameters.
| Symbol | Full name | Definition |
|---|---|---|
CL | CAS Latency | Clock cycles from READ command (CAS) to first valid data on the bus. The most quoted timing. |
tRCD | RAS-to-CAS Delay | Cycles between ACTIVATE command (opens a row) and when a READ or WRITE can be issued. |
tRP | Row Precharge time | Cycles to close the current row (precharge) before a new row can be activated. |
tRAS | Row Active Strobe time | Minimum cycles a row must remain active before it can be precharged. tRAS ≥ CL + tRCD typically. |
Fig 3 — DDR read timing: ACT → (tRCD) → READ → (CL) → Data → PRE → (tRP) → next ACT
Timing specs in cycles only matter relative to the clock period. DDR5-4800 has a clock period of ~0.417 ns. A CL of 40 cycles = 40 × 0.417 ns = 16.7 ns absolute latency — similar to DDR4-3200 CL16 (16 × 0.625 ns = 10 ns). Faster memory doesn't always mean lower absolute latency.
Typical timing specs by generation
| Memory | Speed (MT/s) | CL | tRCD | tRP | Abs. CL latency |
|---|---|---|---|---|---|
| DDR3-1600 | 1600 | 11 | 11 | 11 | ~13.75 ns |
| DDR4-2133 | 2133 | 15 | 15 | 15 | ~14.1 ns |
| DDR4-3200 | 3200 | 16 | 18 | 18 | ~10.0 ns |
| DDR5-4800 | 4800 | 40 | 39 | 39 | ~16.7 ns |
| DDR5-6400 | 6400 | 32 | 36 | 36 | ~10.0 ns |
5. DDR4 vs DDR5 — Key Differences
- 1.2 V operating voltage
- 1600–3200 MT/s
- 8n prefetch
- Single 64-bit channel per DIMM
- No on-die ECC
- External voltage regulation
- Up to 32 Gb per die
- 4 bank groups × 4 banks = 16 banks/chip
- Used in: most desktops/laptops until ~2022
- 1.1 V — lower power
- 4800–8400 MT/s — 2× faster
- 16n prefetch
- Two 32-bit sub-channels per DIMM — better parallelism
- On-die ECC — catches single-bit errors inside the chip
- PMIC on DIMM — voltage regulator on the module
- Up to 64 Gb per die
- 8 bank groups × 4 banks = 32 banks/chip
- Used in: Intel 12th gen+, AMD AM5 Zen 4+
Each DDR5 DIMM presents two independent 32-bit sub-channels to the memory controller (vs DDR4's single 64-bit channel). The controller can issue two independent commands simultaneously — one per sub-channel — doubling command bandwidth and reducing queuing delays, especially for mixed workloads.
6. LPDDR — Low Power DDR
LPDDR (Low Power DDR) is a variant of DDR optimized for mobile and thin client devices — smartphones, tablets, Chromebooks, and thin laptops. The standard is defined by JEDEC and follows a parallel track to standard DDR.
- DIMM form factor — removable, upgradeable
- 1.2 V (DDR4) / 1.1 V (DDR5)
- Wide bus: 64-bit per channel
- Standard self-refresh
- Desktop, workstation, server use
- Higher power — tolerates PSU supply
- Separate voltage regulator (on motherboard)
- Soldered directly to PCB — not removable
- 1.1 V (LPDDR4) / 1.05 V (LPDDR5)
- Narrower per-channel bus, but 2 channels per package
- Partial Array Self-Refresh (PASR) — only refresh used rows
- Smartphones, tablets, thin laptops
- Fine-grained power gating and frequency scaling
- On-package power management
LPDDR generations
| Gen | Year | Voltage | Max speed (MT/s) | Key feature |
|---|---|---|---|---|
| LPDDR3 | 2012 | 1.2 V | 2133 | Low-voltage DDR3 variant for mobile |
| LPDDR4 | 2014 | 1.1 V | 3200 | 2 independent 16-bit channels per package |
| LPDDR4X | 2017 | 1.05 V | 4266 | Extended speed + lower I/O swing |
| LPDDR5 | 2019 | 1.05 V | 6400 | Link ECC, RX DFE, deeper power modes |
| LPDDR5X | 2022 | 1.05 V | 9600 | PAM4 signalling on DQ bus for higher speed |
LPDDR5 adds Deep Sleep and Ultra-Low Power states beyond DDR5's ASPM equivalents. PASR allows the phone's SoC to tell the DRAM to only refresh the portion of array currently holding data — critical for extending battery life during idle/sleep. A flagship phone LPDDR5X package consumes ~1–2W active vs ~0.1mW in deep sleep.
Apple's M-series chips use LPDDR5 dies in a Package-on-Package (PoP) arrangement — DRAM is stacked directly on top of the SoC die inside the same package. The CPU, GPU, and Neural Engine all share this single LPDDR5X pool over a very wide bus (e.g., M3 Max: 300 GB/s). This is why Apple Silicon has such high memory bandwidth without needing GDDR or HBM.
7. Key DDR Signals
| Signal | Direction | Description |
|---|---|---|
CLK / CLK# | Ctrl → DRAM | Differential clock. All commands sampled on the rising edge of CLK. |
CKE | Ctrl → DRAM | Clock Enable. De-asserting puts DRAM into Self-Refresh or Power-Down. |
CS# | Ctrl → DRAM | Chip Select (active low). Selects which rank is being addressed. |
RAS# / CAS# / WE# | Ctrl → DRAM | DDR3 and earlier: command encoding. DDR4/5 replaced with CA[13:0] command-address bus. |
A[15:0] | Ctrl → DRAM | Address bus. Carries row address for ACT, column address for READ/WRITE. |
BA[1:0] | Ctrl → DRAM | Bank Address. Selects which bank to activate/read/write. |
BG[1:0] | Ctrl → DRAM | Bank Group (DDR4+). Selects the bank group for pipelined access. |
DQ[63:0] | Bidirectional | 64-bit data bus. Carries read and write data. Burst length 8 → 512 bits per access. |
DQS / DQS# | Bidirectional | Data Strobe. Differential strobe that accompanies DQ, used to center-align data capture at the receiver. |
DM / DBI# | Ctrl → DRAM | Data Mask / Data Bus Inversion. DM masks write bytes; DBI inverts data bus when majority of bits are 1 to reduce switching current. |
ODT | Ctrl → DRAM | On-Die Termination. Enables internal termination resistors to reduce signal reflections at high frequency. |
ZQ | DRAM pin | Impedance calibration reference pin. Connected to 240Ω to GND; used for automatic output impedance matching. |
8. Refresh — Why DRAM Needs It
DRAM stores each bit as charge in a tiny capacitor. Capacitors leak — without intervention, data is lost in ~64 ms. The memory controller must periodically issue REFRESH commands to recharge all cells.
- Refresh interval tREFI — time between refresh commands: 7.8 μs (standard) or 3.9 μs at high temperature
- Refresh cycle time tRFC — how long a rank is unavailable during refresh: ~350–550 ns for DDR4 depending on die density
- Self-Refresh (SR) — when CKE is de-asserted, the DRAM generates its own refresh internally — no controller involvement. Used during sleep states.
- PASR (LPDDR) — only refresh rows that are actually in use, saving power when memory is partially filled.
Repeatedly reading the same DRAM row (hammering) can cause charge leakage into adjacent rows, flipping bits in a neighbouring row without ever accessing it directly. This is a real security vulnerability exploited to escalate privileges. DDR4 introduced TRR (Targeted Row Refresh) and DDR5 added RFM (Refresh Management) to mitigate it.
9. FAQ
What does DDR stand for?
Double Data Rate. Data is transferred on both the rising and falling edge of the clock signal, giving twice the data rate of an SDR (Single Data Rate) interface at the same clock frequency. Always paired with SDRAM (Synchronous DRAM), so the full name is DDR SDRAM.
What is the difference between DDR4 and DDR5?
Key differences from DDR4 to DDR5:
- Speed: 4800–8400 MT/s (DDR5) vs 1600–3200 MT/s (DDR4)
- Voltage: 1.1 V (DDR5) vs 1.2 V (DDR4)
- Sub-channels: DDR5 splits each DIMM into two 32-bit sub-channels
- On-die ECC in DDR5 (corrects bit errors inside the DRAM chip)
- PMIC on DIMM in DDR5 (voltage regulator moved to the module)
- 16n prefetch in DDR5 vs 8n in DDR4
- 32 banks per chip in DDR5 vs 16 banks in DDR4
What is LPDDR and how does it differ from DDR?
LPDDR (Low Power DDR) is a mobile-optimized variant. Key differences: it is soldered to the PCB (not a removable DIMM), runs at slightly lower voltage (LPDDR5: 1.05 V vs DDR5: 1.1 V), supports Partial Array Self-Refresh (PASR) to only refresh used memory, and has finer-grained power states. It trades some peak bandwidth for significantly lower idle and standby power — critical for battery-powered devices.
What does CL-tRCD-tRP-tRAS mean?
These are the four primary DDR timing parameters, always listed in this order:
- CL — CAS Latency: cycles from READ command to first data
- tRCD — RAS-to-CAS Delay: cycles between ACTIVATE and READ/WRITE
- tRP — Row Precharge: cycles to close a row
- tRAS — Row Active Strobe: minimum cycles a row must stay active
Example: DDR4-3200 rated 16-18-18-38 means CL=16, tRCD=18, tRP=18, tRAS=38 clock cycles.
What is a rank in DDR memory?
A rank is a set of DRAM chips accessed simultaneously to provide one full 64-bit wide data word. A typical DDR4 DIMM with ×8 chips needs 8 chips per rank (8 × 8-bit = 64-bit). A dual-rank DIMM has two such sets — the controller chip-selects between them. Dual-rank improves effective bandwidth by pipelining: while rank 0 precharges, rank 1 can be read.
What is a DIMM and what types exist?
A DIMM (Dual In-line Memory Module) is the physical PCB module that slots into a motherboard. Common types:
- UDIMM — Unbuffered DIMM. Standard desktop and workstation memory. Direct connection to the memory controller.
- RDIMM — Registered DIMM. Has a register (buffer) chip that re-drives address/command signals. Allows more DIMMs per channel. Used in servers.
- LRDIMM — Load-Reduced DIMM. Buffer also re-drives data — allows even more DIMMs. High-capacity server configs.
- SO-DIMM — Small Outline DIMM. Compact form for laptops and mini-PCs.
- LPDDR (on PCB) — Not a DIMM at all — soldered directly to the motherboard in phones and thin laptops.
Why does DRAM need to be refreshed?
DRAM cells store each bit as an electric charge in a tiny capacitor (~20–30 fF). Capacitors leak charge through transistor sub-threshold current — a cell loses enough charge to be unreadable in approximately 64 milliseconds at room temperature (less at higher temperatures). The memory controller issues REFRESH commands every 7.8 μs to cycle through all rows and recharge them before data is lost. During a refresh, the rank is unavailable for ~350–550 ns.
What is HBM and how does it relate to DDR?
HBM (High Bandwidth Memory) is a different DRAM packaging technology — DRAM dies are stacked vertically (3D stacking) directly on or very close to the processor using silicon interposer. It uses the same DRAM cell technology as DDR but with a much wider bus (1024 bits per stack vs 64-bit for DDR) and much shorter traces for extremely high bandwidth (e.g., HBM3: >1 TB/s). Used in NVIDIA H100, AMD Instinct MI300X, and Intel Ponte Vecchio for AI/HPC. Not used in standard consumer PCs due to cost.