Design for Test (DFT)

1. Why DFT Matters

A fabricated chip can fail not because of design errors, but because of manufacturing defects: tiny particles of contamination, variations in oxide thickness, or etch imperfections that create unintended shorts (bridging faults), opens, or incorrect logic levels. These are random and unpredictable — they cannot be simulated before fabrication.

Without DFT, only the primary inputs and outputs of the chip are accessible to an external tester. The internal state of millions of flip-flops is invisible, and the vast majority of gates cannot be exercised to detect defects. Industry targets for test coverage:

2. Scan Insertion

Scan insertion replaces standard D flip-flops with scan flip-flops (SFF), which add two ports: SI (scan input) and SE (scan enable). When SE = 1, the FF's D input is disconnected and replaced by SI, forming a shift register. When SE = 0, the FF operates normally.

All SFFs are chained together into one or more scan chains. During test:

1. Scan shift in (SE=1): Clock the test pattern into the chain bit by bit through SI
2. Capture (SE=0, one clock cycle): Apply the loaded pattern functionally, capturing the circuit's response into the SFFs
3. Scan shift out (SE=1): Shift the captured response out through SO to the tester
4. Compare captured response to expected values; any difference = detected fault

3. Fault Models

A fault model is an abstraction of a physical defect. ATPG generates patterns to detect faults defined by the model:

4. ATPG — Automatic Test Pattern Generation

ATPG automatically generates the minimum set of test patterns that maximizes fault coverage. The two core operations for any ATPG algorithm are:

• Justification (excitation): Drive the primary inputs (or scan-loaded values) such that the fault site takes the faulty value — e.g., set a net to 0 to detect SA1 at that net.
• Propagation (observation): Find a sensitized path from the fault site through combinational logic to a primary output or a scannable FF where the faulty value can be observed.

Classical ATPG algorithms

• D-algorithm (1966): Uses D and D̄ symbols to represent fault effects. Complete but slow — exponential worst-case.
• PODEM (1981): Path Oriented DEcision Making. Works backward from the fault site. More practical for large circuits.
• FAN (1983): FAN-out Oriented. Identifies fan-out stems and frontiers to prune the search space. Industry-standard for stuck-at.

# Define DFT scan signals (Synopsys DC / Fusion Compiler)
set_dft_signal -view existing_dft \
  -type ScanEnable \
  -port SE

set_dft_signal -view existing_dft \
  -type ScanDataIn \
  -port scan_in[*]

# Preview DFT insertion (dry run)
preview_dft -show scan_summary

# Insert DFT (replaces FFs with scan FFs)
insert_dft

# Write scan definition file for ATPG tool
write_scan_def -output scan.def

# In Synopsys TetraMAX / Mentor FastScan: run ATPG
run_atpg \
  -fault_type stuck \
  -effort high \
  -target_coverage 98

5. BIST — Built-In Self Test

LBIST (Logic BIST)

LBIST embeds a pseudo-random pattern generator (PRPG) and a multiple-input signature register (MISR) on-chip. The PRPG generates many random patterns (typically 100,000–1,000,000) and feeds them into the scan chains. The MISR compresses all captured responses into a single signature. After the test completes, the signature is compared to the expected golden value. A mismatch means at least one fault was detected.

MBIST (Memory BIST)

SRAMs require dedicated MBIST because standard ATPG cannot access internal memory cells. MBIST runs march algorithms — systematic sequences of read/write operations that detect stuck-at, coupling, transition, and address decoder faults:

• March C−: Writes all-0, reads 0/writes 1 upward, reads 1/writes 0 downward. Detects stuck-at and coupling faults.
• Checkerboard: Writes alternating 0/1 pattern. Detects weak cells at boundaries.

6. JTAG / Boundary Scan (IEEE 1149.1)

JTAG (Joint Test Action Group) defines a standardized serial test interface present on almost every modern chip. Four mandatory signals: TCK (test clock), TMS (test mode select), TDI (test data in), TDO (test data out), plus optional TRST (reset).

TAP Controller

The Test Access Port (TAP) controller is a 16-state state machine driven by TCK and TMS. Key states: Test-Logic-Reset, Run-Test/Idle, Shift-DR, Shift-IR, Update-DR, Update-IR. The controller manages routing TDI/TDO to either the instruction register (IR) or data registers (DR).

Boundary scan cells

Each chip I/O pin has a boundary scan cell (BSC) — a small register that can capture the pin's logic value or force it to a specific value. The BSCs form the Boundary Scan Register (BSR), chained from TDI to TDO. JTAG instructions:

• EXTEST: Forces BSR values onto board-level outputs. Tests board interconnects between chips.
• INTEST: Tests internal chip logic by applying patterns through the BSR to internal logic.
• SAMPLE/PRELOAD: Captures I/O values non-disruptively; used for bring-up debugging.