What is the setup slack equation?

Setup slack = Required Arrival Time - Actual Arrival Time. Required Arrival Time = (launch clock edge + clock period) - setup time - capture clock latency. Actual Arrival Time = launch clock latency + clock-to-Q delay + combinational logic delay. Positive slack means timing is met; negative slack is a setup violation.

How do you fix a setup violation?

Fix strategies for setup violations: (1) Upsize logic cells to faster (lower drive strength) variants or switch to LVT cells. (2) Remove redundant logic on the critical path. (3) Add pipeline registers to break long combinational paths. (4) Use clock skew intentionally (useful skew) to borrow time. (5) Increase the clock period (reduce frequency) if all else fails.

How do you fix a hold violation?

Fix strategies for hold violations: (1) Insert delay buffers on the data path. (2) Use higher-drive or HVT cells which are slower. (3) Increase wire length (add net detours) — though this is a last resort. Hold violations introduced during CTS (when real clock tree delays differ from ideal) are fixed by the PnR tool during post-CTS optimization.

DAY 2 · STA FUNDAMENTALS

Setup Time & Hold Time — The Physics and the Math

Q: What is setup time in a flip-flop?

Setup time (Tsu) is the minimum time the data input (D) must be stable before the active clock edge. If data arrives later than Tsu before the clock edge, the flip-flop enters a metastable state and may produce an unpredictable output. Setup time is a fundamental property of the flip-flop cell, specified in the Liberty library.

Q: What is hold time in a flip-flop?

Hold time (Th) is the minimum time the data input must remain stable after the active clock edge. If data changes too soon after the clock edge, the flip-flop may again enter metastability. Hold time is independent of the clock period — it is always checked for every flip-flop regardless of frequency.

By EcrioniX · Updated June 2026

Setup time and hold time are the two constraints every flip-flop imposes on the data arriving at its D pin. Getting these wrong — even by a few picoseconds — causes metastability: the flip-flop output goes to an undefined voltage level and can corrupt an entire chip. This lesson explains what they mean physically, derives the slack equations from first principles, and shows how to fix violations.

1. Inside a flip-flop — what actually happens

A flip-flop is built from two cross-coupled latches (master and slave). When the clock is low, the master latch is transparent and tracks the D input. When the clock goes high, the master latch closes (locks the value) and the slave latch opens (propagates Q).

For the master latch to close reliably, D must have settled to a stable logic level before the clock rises. Setup time (T_su) is how long before the clock edge D must be stable. After the clock rises, D must hold stable long enough for the feedback inside the master latch to fully resolve. Hold time (T_h) is how long after the clock edge D must remain unchanged.

Figure — Setup and hold time windows around the active clock edge. Data must be stable throughout the shaded regions.

2. The slack equations

STA computes two slack values at each flip-flop: setup slack and hold slack. Both must be non-negative for the design to meet timing.

Setup Slack = (T_clk + T_{capture_clk} − T_su) − (T_{launch_clk} + T_clk2q + T_comb)

— simplified as —

Setup Slack = Required Time − Arrival Time

Hold Slack = (T_{launch_clk} + T_clk2q + T_comb) − (T_{capture_clk} + T_h)

— simplified as —

Hold Slack = Arrival Time − (Hold Required Time)

Term definitions

Term	What it means
T_clk	Clock period (e.g. 2 ns for a 500 MHz clock)
T_{launch_clk}	Clock latency to the launch flip-flop (source clock + clock tree delay to FF1)
T_{capture_clk}	Clock latency to the capture flip-flop (source clock + clock tree delay to FF2)
T_clk2q	Clock-to-Q propagation delay of the launch FF (Q stable after clock edge)
T_comb	Combinational logic delay between FF1 output and FF2 data input
T_su	Setup time requirement of the capture FF (from Liberty library)
T_h	Hold time requirement of the capture FF (from Liberty library)

Clock skew changes both slacks simultaneously

Clock skew = T_{capture_clk} − T_{launch_clk}. Positive skew (capture clock arrives later) helps setup slack but hurts hold slack. Negative skew (capture clock arrives earlier) hurts setup but helps hold. This is why setup and hold violations cannot both be fixed by changing clock arrival times — fixing one can break the other.

3. Worked example

A register-to-register path with the following parameters:

Parameter	Value
Clock period (T_clk)	4 ns
Launch clock latency (T_{launch_clk})	0.5 ns
Capture clock latency (T_{capture_clk})	0.6 ns
Clock-to-Q delay (T_clk2q)	0.2 ns
Combinational delay (T_comb)	2.8 ns
Setup time (T_su)	0.15 ns
Hold time (T_h)	0.05 ns

Setup slack calculation

Arrival Time  = T_launch_clk + T_clk2q + T_comb
              = 0.5 + 0.2 + 2.8 = 3.5 ns

Required Time = T_clk + T_capture_clk - T_su
              = 4.0 + 0.6 - 0.15 = 4.45 ns

Setup Slack   = Required Time - Arrival Time
              = 4.45 - 3.5 = +0.95 ns  ✓ PASS

Hold slack calculation

Arrival Time      = T_launch_clk + T_clk2q + T_comb
                  = 0.5 + 0.2 + 2.8 = 3.5 ns

Hold Required     = T_capture_clk + T_h
                  = 0.6 + 0.05 = 0.65 ns

Hold Slack        = Arrival Time - Hold Required
                  = 3.5 - 0.65 = +2.85 ns  ✓ PASS

4. What causes violations

Setup violations

Data arrives too late at the capture FF. The combinational path is too slow — too many logic levels, large fanout, long wires, slow cells, or a high PVT (slow process corner, low voltage, high temperature) operating condition.

Classic sign: negative setup slack on the longest combinational paths. Worsens as frequency increases.

Hold violations

Data arrives too fast at the capture FF — before the capture clock edge has settled the previous value. Common after CTS when real clock tree delays replace ideal zero-latency clocks. Short paths between consecutive FFs are most at risk.

Classic sign: negative hold slack on very short data paths. Hold violations are frequency-independent — they exist at any clock speed.

5. Fix strategies

Fixing setup violations

Upsize cells on the critical path to faster/stronger variants
Switch to LVT cells (Low-Vt threshold — faster but higher leakage)
Remove logic levels via synthesis re-mapping or manual restructuring
Pipeline the path — add a register to break a long combinational chain
Reduce fanout by cloning or buffering high-fanout nets
Useful skew — delay the capture clock slightly to give data more time

Fixing hold violations

Insert delay buffers (or delay cells) on the short data path
Downsize cells to slower HVT variants
Add wire detours to increase net delay (last resort)
Fix clock skew — balance the clock tree so capture clock arrives earlier
PnR tool auto-fixes most hold violations post-CTS via ECO buffer insertion

Hold violations must never be waived

A setup violation means the chip may fail at high frequency — you can reduce the clock. A hold violation causes corruption at any frequency and cannot be fixed by slowing down. Every hold violation must be fixed before tapeout, no exceptions.

6. Checking setup and hold in PrimeTime

report_timing — setup and hold checks

## Setup check (max delay analysis) -- worst 5 violating paths
report_timing -delay_type max \
              -max_paths 5 \
              -slack_lesser_than 0 \
              -path_type full_clock_expanded

## Hold check (min delay analysis) -- worst 5 violating paths
report_timing -delay_type min \
              -max_paths 5 \
              -slack_lesser_than 0 \
              -path_type full_clock_expanded

## Quick summary: WNS and TNS for both checks
report_timing_summary

## Check a specific path from FF1/CK to FF2/D
report_timing -from FF1/CK -to FF2/D -delay_type max

Reading the timing report

The timing report lists: startpoint (launch FF clock pin), endpoint (capture FF data pin), path type (max=setup / min=hold), arrival time, required time, and slack. Negative slack = violation. The path with the worst (most negative) slack is the critical path. Day 11 covers reading full PrimeTime reports line-by-line.

Day 2 Key Takeaways

Setup time — data must be stable T_su before the clock edge; violation = data arrives too late
Hold time — data must stay stable T_h after the clock edge; violation = data arrives too fast
Setup slack = Required Time − Arrival Time — checked with -delay_type max
Hold slack = Arrival Time − Hold Required Time — checked with -delay_type min
Positive skew helps setup, hurts hold; negative skew does the opposite
Fix setup: upsize/LVT cells, remove logic, pipeline, useful skew
Fix hold: insert delay buffers — never waive hold violations
Hold violations are frequency-independent and mandatory to fix before tapeout

Frequently Asked Questions

What is setup time in a flip-flop?

Setup time (T_su) is the minimum time the D input must be stable before the active clock edge. If data arrives inside this window, the flip-flop may enter metastability — its output goes to an undefined voltage and may take nanoseconds to resolve. Setup time is specified per cell in the Liberty library.

What is hold time in a flip-flop?

Hold time (T_h) is the minimum time D must remain stable after the active clock edge. Violating hold causes the same metastability problem as setup. Hold time is independent of clock period — it must be met at any frequency, which is why hold violations cannot be fixed by reducing clock speed.

Why does positive clock skew help setup but hurt hold?

Positive skew means the capture FF's clock arrives later than the launch FF's clock. This gives the data path more time to propagate (improving setup margin). But it also means the capture FF's clock edge is delayed relative to the data path — making it easier for a new data value (from the next cycle) to arrive before the current one is safely captured (degrading hold margin).

What is the difference between setup time and propagation delay?

Propagation delay is the time for a signal to travel through a logic gate or wire — it adds to the data arrival time. Setup time is a requirement on the flip-flop's data pin — it reduces the time budget available for the data path. Both appear in the setup slack equation: a longer propagation delay or a larger setup time requirement both reduce setup slack.

At what stage are hold violations typically introduced?

Hold violations are frequently introduced during Clock Tree Synthesis (CTS). Before CTS, STA uses ideal (zero-latency) clocks, which makes all paths appear symmetric. After CTS, real clock tree delays mean some paths have large clock skew. Short data paths between FFs with high positive skew are the most common hold violation source post-CTS.