What is the critical path?

The critical path is the timing path with the worst (most negative) setup slack. It defines the maximum operating frequency of the design. Fmax = 1 / (Tclk_min), where Tclk_min is the minimum clock period that keeps all setup slacks non-negative. Timing closure involves iteratively fixing the critical path until all paths meet timing.

What is arrival time in STA?

Arrival time at a node is the earliest (or latest) time a signal can arrive at that node, measured from the clock edge. STA propagates arrival times forward through the timing graph: arrival_time(output) = arrival_time(input) + cell_delay + net_delay. The final arrival time at an endpoint is compared against the required time to compute slack.

DAY 3 · STA FUNDAMENTALS

Timing Paths — Startpoints, Endpoints, and Slack

Q: What is an endpoint in STA?

An endpoint is where STA finishes tracing a path and checks timing. Valid endpoints are: (1) the data pin (D) of a flip-flop — checked for setup and hold against the capture clock edge, (2) a primary output port — checked against set_output_delay constraints. Every endpoint must have positive setup and hold slack for timing to be met.

Q: What is a timing arc?

A timing arc is the delay between two pins in the timing graph. Every standard cell in the Liberty library defines timing arcs for each input-to-output combination and their delays (which vary with input transition time and output capacitance load). Net arcs carry the interconnect delay from a driver pin to a receiver pin.

By EcrioniX · Updated June 2026

Everything in STA revolves around timing paths. A timing path is a directed route through the circuit from a startpoint to an endpoint. The STA tool enumerates every possible path, computes the total delay along each one, and checks whether the signal arrives within the required window. Understanding how paths are traced, how arrival time is computed, and what makes a path critical is the foundation for all timing closure work.

1. Startpoints and endpoints

A timing path always runs from a startpoint to an endpoint. STA defines these precisely:

Role	Valid elements	What STA does here
Startpoint	Clock pin of a flip-flop (CK), primary input port	Initialises arrival time; data launches on this clock edge
Endpoint	Data pin of a flip-flop (D), primary output port	Checks timing; computes slack = required − arrival

Between startpoint and endpoint, the path passes through combinational logic: AND gates, OR gates, muxes, adders, and the interconnect (wires) between them. STA traverses this logic as a directed acyclic graph (DAG), accumulating delay at every node.

Why clock pins are startpoints, not Q pins

The data launches from the flip-flop on the clock edge. STA models this as: at the clock edge, a new value appears at Q after clock-to-Q delay (T_clk2q). The path then starts propagating from Q through combinational logic. So the startpoint is the CK pin, and T_clk2q is the first delay segment in the path.

2. Timing arcs — where delays come from

Every delay in a timing path comes from one of two sources:

Cell arc — delay through a standard cell from one pin to another (e.g. AND gate input A to output Z). Defined in the Liberty library as a function of input transition time and output load capacitance.
Net arc — delay from the driver output pin to the receiver input pin through the wire. Computed from the RC parasitics in the SPEF file after physical layout.

Pre-layout STA uses estimated net delays (wireload models). Post-layout STA uses actual extracted parasitics — this is why post-layout timing differs from synthesis timing.

3. How arrival time propagates

STA propagates arrival time forward from every startpoint using a simple rule at each node:

Arrival Time(output) = Arrival Time(input) + Cell Delay + Net Delay

For a gate with multiple inputs (e.g. AND2), STA takes the worst arrival time across all inputs when computing the output arrival time — because the output cannot be driven until all inputs have settled.

Launch clock propagation

Propagate clock arrival from the source (PLL/oscillator) through the clock buffer tree to the CK pin of the launch FF. This is T_{launch_clk}.

Clock-to-Q

Add T_clk2q (the FF’s own output delay after the clock edge). Arrival at Q = T_{launch_clk} + T_clk2q.

Combinational logic traversal

For each cell and net in the path, add cell delay and net delay. At multi-input gates, take the latest arriving input.

Arrival at endpoint

The final accumulated value is the data arrival time at the capture FF’s D pin.

4. Required time and slack

For setup analysis, the required time at the endpoint D pin is the latest the data can arrive and still be captured reliably:

Required Time = T_clk + T_{capture_clk} − T_su

( next clock edge + capture clock latency − setup time requirement )

Setup Slack = Required Time − Arrival Time

For hold analysis, the required time is the earliest the data is allowed to arrive (it must not arrive before the capture FF has safely stored the previous value):

Hold Required Time = T_{capture_clk} + T_h

Hold Slack = Arrival Time − Hold Required Time

5. A complete worked path example

Figure — A reg-to-reg timing path. Green arrows show the data path. Dashed purple lines show clock delivery. Numbers are delays in nanoseconds.

Arrival time computation for the path above

Startpoint : FF1/CK (clock pin of FF1)
Endpoint   : FF2/D  (data pin of FF2)

-- Clock path (launch) --
  Clock source                    :  0.00 ns
  Clock buffer tree to FF1 (CK)   :  0.50 ns   <- T_launch_clk
  FF1 clock-to-Q (T_clk2q)       :  0.20 ns
  Subtotal (data starts here)     :  0.70 ns

-- Data path --
  Net:  FF1/Q -> AND2/A           :  0.10 ns
  Cell: AND2 (A->Z)               :  0.35 ns
  Net:  AND2/Z -> OR2/A           :  0.12 ns
  Cell: OR2 (A->Z)                :  0.28 ns
  Net:  OR2/Z -> INV/A            :  0.08 ns
  Cell: INV (A->ZN)               :  0.18 ns
  Net:  INV/ZN -> FF2/D           :  0.10 ns

Data Arrival Time at FF2/D        :  1.91 ns

-- Required time (setup) --
  Next clock edge                 :  4.00 ns   (250 MHz clock)
  Clock buffer tree to FF2 (CK)   :  0.60 ns   <- T_capture_clk
  Setup time (T_su) [library]     : -0.15 ns
  Required Time                   :  4.45 ns

Setup Slack = 4.45 - 1.91 = +2.54 ns  (PASS)

6. Finding the critical path

The critical path is the path with the worst (most negative) setup slack — the path that most constrains the maximum clock frequency. Once fixed, the next-worst path becomes the new critical path. This is why timing closure is iterative.

F_max = 1 / (T_{launch_clk} + T_clk2q + T_{comb_max} + T_su − T_{capture_clk})

Maximum operating frequency — determined by the longest combinational path

Finding worst paths in PrimeTime

## Top 20 worst setup paths across all endpoints
report_timing -max_paths 20 \
              -delay_type max \
              -sort_by slack

## Top 10 worst paths in a specific clock domain
report_timing -max_paths 10 \
              -delay_type max \
              -group clk_core

## Show full path detail for the single worst path
report_timing -delay_type max \
              -nworst 1 \
              -path_type full_clock_expanded

## Quick WNS/TNS summary
report_timing_summary

7. Path types recap

Path Type	Startpoint	Endpoint	Constrained by
Reg-to-Reg	FF clock pin (CK)	FF data pin (D)	Clock period (create_clock)
Input-to-Reg	Primary input port	FF data pin (D)	set_input_delay
Reg-to-Output	FF clock pin (CK)	Primary output port	set_output_delay
Input-to-Output	Primary input port	Primary output port	set_input_delay + set_output_delay

Paths STA ignores by default

Paths between asynchronous clocks (no defined phase relationship) are reported as unconstrained — they require set_clock_groups -asynchronous or CDC analysis instead. Paths explicitly excluded with set_false_path are ignored. Paths with set_multicycle_path N are checked against N × Tclk instead of 1 × Tclk. Day 4 (SDC) covers these constraints in detail.

Day 3 Key Takeaways

Startpoints: FF clock pins (CK) and primary input ports — where arrival time is initialised
Endpoints: FF data pins (D) and primary output ports — where slack is computed
Arrival time propagates forward: AT(output) = AT(input) + cell_delay + net_delay
At multi-input gates, take the worst (latest) arriving input
Required time = T_clk + T_{capture_clk} − T_su (for setup)
Slack = Required − Arrival (setup) or Arrival − Hold Required (hold)
Critical path = worst setup slack — sets F_max; timing closure fixes these iteratively
Use report_timing -sort_by slack to find worst paths quickly in PrimeTime

Frequently Asked Questions

What is a startpoint in STA?

A startpoint is where STA begins tracing a timing path. Valid startpoints are the clock pin (CK) of a flip-flop — the most common — and primary input ports. The STA tool initialises the arrival time at each startpoint and propagates it forward through the combinational logic to the endpoint.

What is an endpoint in STA?

An endpoint is where STA checks timing and computes slack. Valid endpoints are the data pin (D) of a flip-flop and primary output ports. Every endpoint must have non-negative setup slack and non-negative hold slack for the design to meet timing.

What is a timing arc?

A timing arc is the elementary delay between two pins — either through a logic cell (cell arc) or through a wire (net arc). Cell arcs are defined in the Liberty library and depend on input slew and output load. Net arcs are computed from parasitic RC values extracted from the physical layout (SPEF).

Why does STA take the worst arrival time at multi-input gates?

A logic gate cannot produce a stable output until all its inputs have settled. Therefore the output arrival time is determined by the last input to arrive. STA conservatively uses the worst (latest) input arrival time to compute the output arrival time, ensuring all paths are checked under the worst case.

What is the difference between pre-layout and post-layout STA?

Pre-layout (pre-route) STA estimates wire delays using wireload models — statistical estimates based on fanout and design size. Post-layout STA uses actual parasitic RC values extracted from the placed-and-routed netlist (SPEF). Post-layout timing is more accurate and is the sign-off standard; pre-layout timing gives faster but less precise feedback during synthesis and early floorplanning.