A chip that passes timing at nominal conditions may fail catastrophically in the field. Process variation means your silicon might be slow. Low battery means voltage droops. High ambient temperature makes transistors sluggish. PVT corner analysis — and its industrial-scale version, MCMM — ensures your chip meets timing at every extreme it will realistically encounter.
Every chip operates across a range of conditions. STA captures this by running separate analyses at the corners of the PVT space:
Semiconductor manufacturing has inherent variability. Even on the same wafer, transistors can be faster or slower than the target due to lithographic variation, doping concentration differences, and gate oxide thickness. The foundry characterises this as process corners:
SS and FF are the critical corners for timing sign-off. SF/FS are sometimes run for SRAM access timing and other technology-specific checks.
A lower supply voltage slows transistors down (gate overdrive decreases). Higher voltage speeds them up. Voltage also droops transiently due to IR drop as large blocks switch simultaneously. The voltage range is specified by the chip’s datasheet and the regulator accuracy:
Temperature effects on timing are more nuanced than voltage. At high temperature, carrier mobility decreases, slowing transistors. However, at very low temperatures, subthreshold leakage dominates and behaviour can reverse. For CMOS at typical voltages:
At 28nm and below with low supply voltages, cold temperature can actually make gates slower due to threshold voltage increase dominating over mobility. This “temperature inversion” effect means some foundries now run SS/0.9V/-40C as an additional setup corner. Always follow your PDK’s recommended corner table.
| Corner Name | Process | Voltage | Temperature | Primary Check | Why? |
|---|---|---|---|---|---|
| SS/0.9V/125C | Slow-Slow | 0.9V (low) | 125°C (hot) | Setup sign-off | Gates are slowest; data paths take longest |
| FF/1.1V/-40C | Fast-Fast | 1.1V (high) | −40°C (cold) | Hold sign-off | Gates are fastest; data can arrive before hold window closes |
| TT/1.0V/25C | Typical | 1.0V (nominal) | 25°C (room) | Functional verification | Nominal conditions; used for power analysis and simulation correlation |
| SS/0.9V/-40C | Slow-Slow | 0.9V | −40°C | Cold-corner setup (sub-28nm) | Temperature inversion: cold can be slower at low voltage |
| FF/1.1V/125C | Fast-Fast | 1.1V | 125°C | Leakage/power | Worst-case leakage current for power sign-off |
| Timing element | SS corner effect | FF corner effect |
|---|---|---|
| Combinational gate delay | Increases (slower transistors) | Decreases (faster transistors) |
| Clock-to-Q delay (flip-flop) | Increases | Decreases |
| Setup time requirement | Increases (flip-flop is slower) | Decreases |
| Hold time requirement | Decreases (less of a threat) | Increases (flip-flop captures faster, needs data to hold longer) |
| Wire delay (RC) | Higher resistance at hot temp | Lower resistance at cold temp |
| Clock skew | Higher (buffers have more delay variation) | Lower (less variation) |
In SDC (and in PrimeTime directly), you tell the tool which corner to use with set_operating_conditions. This selects the matching condition from the Liberty file’s operating_conditions block.
## Use the slow-slow corner for setup analysis ## Library must be loaded: sc9_ss_0p9v_125c.lib set_operating_conditions -max "ss_0p9v_125c" \ -max_library sc9_ss_0p9v_125c ## For hold, use fast-fast set_operating_conditions -min "ff_1p1v_n40c" \ -min_library sc9_ff_1p1v_n40c ## Typical-Typical for functional verification set_operating_conditions "typical" \ -library sc9_tt_1p0v_25c ## Dual-corner in one PT session (for simultaneous setup+hold) ## read_lib loads both files read_lib sc9_ss_0p9v_125c.lib read_lib sc9_ff_1p1v_n40c.lib set_operating_conditions \ -max "ss_0p9v_125c" -max_library sc9_ss_0p9v_125c \ -min "ff_1p1v_n40c" -min_library sc9_ff_1p1v_n40c
In a real design flow, a chip has not just multiple PVT corners but also multiple functional modes. A mobile SoC might have a high-performance mode (all blocks running at maximum frequency), a low-power mode (clock gating and frequency scaling), a test/scan mode, and a sleep mode. Each mode can have a different clock frequency, different clock enables, and different constraints.
MCMM (Multi-Corner Multi-Mode) runs STA across all combinations of corners and modes simultaneously. The tool maintains separate constraint scenarios and timing graphs for each combination, then reports the worst-case slack across all of them. This eliminates the manual process of running separate STA sessions per corner and manually comparing results.
## ── Step 1: Load all corner Liberty files ── read_lib sc9_ss_0p9v_125c.lib read_lib sc9_ff_1p1v_n40c.lib read_lib sc9_tt_1p0v_25c.lib ## ── Step 2: Load netlist (shared across all scenarios) ── read_verilog top_netlist.v link_design TOP ## ── Step 3: Create scenarios ── ## Scenario 1: Functional mode, SS corner (setup check) create_scenario func_ss_setup set_scenario_options -setup true -hold false set_operating_conditions -max ss_0p9v_125c \ -max_library sc9_ss_0p9v_125c source func_mode.sdc ## Scenario 2: Functional mode, FF corner (hold check) create_scenario func_ff_hold set_scenario_options -setup false -hold true set_operating_conditions -min ff_1p1v_n40c \ -min_library sc9_ff_1p1v_n40c source func_mode.sdc ## Scenario 3: Scan mode, SS corner create_scenario scan_ss_setup set_scenario_options -setup true -hold false set_operating_conditions -max ss_0p9v_125c \ -max_library sc9_ss_0p9v_125c source scan_mode.sdc ## ── Step 4: Run timing analysis across all scenarios ── update_timing -full report_timing_summary ; ## worst WNS/TNS per scenario ## ── Step 5: Report worst case ── report_global_timing -significant_digits 4
Not every possible corner combination needs to be run. The engineering team selects corners based on what is likely to be limiting. A practical set for a 28nm mobile SoC:
The most common mistake made by first-time ASIC engineers is running STA only at TT and declaring timing clean. A chip that passes at TT may have 20% slack violation at SS/low-V/hot. Sign-off requires WNS ≥ 0 at the slow corner for setup, and WNS ≥ 0 at the fast corner for hold, across all modes.
Each corner may also apply timing derating factors (OCV) on top of the Liberty delay. These are multiplicative scaling factors that account for within-die variation:
PVT corners are the extreme combinations of Process (SS/TT/FF silicon speed), Voltage (low/nominal/high supply), and Temperature (hot/room/cold) that a chip will experience in the field. STA must pass at every corner to guarantee timing correctness across the chip’s full operating range.
SS/low-voltage/hot corner makes gates slowest, causing data paths to be longest — this is when setup violations occur. FF/high-voltage/cold makes gates fastest, causing data to arrive so quickly that it violates the capture flip-flop’s hold time requirement. Each corner stresses a different timing check.
MCMM (Multi-Corner Multi-Mode) is the practice of running STA simultaneously across all PVT corners and all operational modes of the design. A modern MCMM run might cover 18–30 scenarios (6 corners × 3–5 modes). The tool finds the worst-case violating path across all scenarios and reports a unified result.
It tells the STA tool which PVT corner the current analysis represents, selecting the correct Liberty delay tables. Without it, the tool uses the default condition in the Liberty file. For MCMM, each scenario has its own set_operating_conditions pointing to a different Liberty file.
Typical ASIC tape-out requires 8–20+ scenarios. At minimum: SS setup corner, FF hold corner, TT functional corner. Advanced flows add cold-corner setup, temperature inversion corners, leakage corners, and multiple voltage-island combinations. All must show WNS ≥ 0 and TNS = 0.