Standard STA models each net in isolation. But on a real chip, nets run parallel to each other in dense metal routing, separated by only a few nanometres of dielectric. When one net switches, it capacitively couples onto its neighbours. This crosstalk can slow or speed up signals (delta delay), or inject voltage pulses onto quiet nets (glitch) — both of which can cause failures that standard STA would not predict.
Two parallel metal wires form a capacitor between them. When wire A (the aggressor) switches, current flows through this coupling capacitor into wire B (the victim). The amount of induced current depends on:
When the aggressor switches while the victim is also switching, the induced current either adds to or subtracts from the victim’s drive current:
| Aggressor direction | Victim direction | Delta delay effect | Impact on timing |
|---|---|---|---|
| Rising (0→1) | Rising (0→1) | Negative delta — victim transitions faster | Helps setup, hurts hold (data arrives early) |
| Falling (1→0) | Falling (1→0) | Negative delta — victim transitions faster | Helps setup, hurts hold |
| Rising (0→1) | Falling (1→0) | Positive delta — victim transitions slower | Hurts setup, helps hold (data arrives late) |
| Falling (1→0) | Rising (0→1) | Positive delta — victim transitions slower | Hurts setup, helps hold |
For setup analysis, STA looks for the worst-case combination of aggressor and victim transitions that maximise the victim’s delay (positive delta = opposite-direction switching). For hold analysis, it looks for the combination that minimises delay (negative delta = same-direction switching).
A glitch occurs when the victim net is not switching but the aggressor is. The aggressor injects charge through Cc, momentarily raising or lowering the victim voltage. The glitch amplitude is approximately:
V_glitch ≈ VDD × Cc / (Cc + Cground)
Where Cground is the victim’s ground capacitance (total net load). If Cc is large relative to Cground — possible on long parallel runs with weak victim drivers — the glitch can exceed the logic threshold and cause false capture at a downstream flip-flop. This is a functional failure, not just a timing one.
A glitch-induced capture looks like a random bit flip. It may only occur when a specific aggressor switching pattern coincides with a vulnerable victim state. These failures are sensitive to timing (which cycle the aggressor switches on) and are extremely difficult to reproduce in simulation. SI analysis in STA catches them before silicon.
Standard PrimeTime reads coupling capacitance from SPEF files (the post-layout parasitics). Coupling caps are in the SPEF as *C *NET victim_net 0.xxx fF aggressor_net 0.yyy fF entries. In SI mode, PT performs:
When SI is enabled, the PrimeTime timing report includes an additional delta column showing the crosstalk contribution per net segment. The total delta on a critical path can easily add 50–200ps at 28nm.
The physical fixes for crosstalk address the coupling capacitance, the aggressor slew rate, or the victim net’s susceptibility:
| Fix technique | How it works | Cost | Best for |
|---|---|---|---|
| Shielding | Insert a GND or VDD wire between aggressor and victim; Cc to shield is much lower than Cc to aggressor | High area (needs extra routing track) | Clock tree nets, critical data paths |
| Spacing | Increase physical distance between aggressor and victim; Cc drops with distance | Medium (needs re-routing) | Nets with long parallel runs |
| Buffer insertion on victim | Break victim net into shorter segments; reduces high-impedance segment length | Low–medium (area for buffer) | Long weak-drive victim nets |
| Layer change | Re-route aggressor or victim to a different metal layer (often with ground plane below) | Medium (routing congestion impact) | Clock vs data on parallel layers |
| Driver upsizing on victim | Stronger driver lowers victim net impedance; harder to inject glitch | Medium (area, power) | Glitch violations on low-drive nets |
| Reducing aggressor slew | Slow down aggressor transitions; less dV/dt = less induced current | Low (timing impact on aggressor path) | When aggressor is not timing-critical |
A SPEF file for SI must include coupling capacitance lines (marked with coupling net names, not just total cap to ground). If your extraction flow only extracts ground capacitance (total cap model), SI analysis cannot be performed correctly. Ensure your extraction tool is run with -coupling or equivalent option. The percentage of coupling vs total cap grows significantly at 28nm and below — often 40–60% of total cap is coupling.
Crosstalk occurs when a switching aggressor net capacitively couples noise onto an adjacent victim net. It causes two effects: delta delay (the victim transition is sped up or slowed down) and crosstalk glitch (a spurious voltage pulse on a quiet victim that can cause a logic error). Standard STA ignores crosstalk; Signal Integrity (SI) analysis extends STA to model it.
Delta delay is the timing deviation on a victim net caused by an aggressor switching simultaneously. Same-direction switching (both nets rising or falling) speeds up the victim (negative delta), which helps setup but hurts hold. Opposite-direction switching slows the victim (positive delta), which hurts setup but helps hold. SI-aware STA computes the worst-case delta for each victim in each timing check direction.
A glitch is a momentary voltage pulse induced on a victim net that is not switching. When an aggressor switches rapidly with significant coupling capacitance to a quiet victim, charge is injected into the victim. If the glitch exceeds the logic threshold of a downstream cell, it may be incorrectly captured as a logic transition, causing a functional failure even though no timing path was violated.
In SI mode, PrimeTime reads coupling capacitances from SPEF, identifies aggressor nets for each victim, determines worst-case simultaneous switching scenarios, computes the delta delay for each victim net segment, and adds it to the standard path delay. It also performs glitch analysis. The results are visible in the timing report as a delta column per net segment.
The primary fixes are: (1) shielding — inserting a GND/VDD wire between aggressor and victim to interrupt Cc; (2) spacing — increasing physical distance; (3) buffer insertion on the victim to break high-impedance segments; (4) layer change to route on a layer with a ground plane; (5) driver upsizing on the victim to lower its impedance and reduce glitch amplitude.