The clock network is the backbone of every synchronous design. Every flip-flop’s timing requirement is measured relative to when its clock edge actually arrives — and that arrival time is determined by the clock tree. Skew, jitter, and latency aren’t abstractions: they directly eat into your setup and hold margins. Understanding how STA models the clock tree is essential for reading any real timing report.
The total delay from the clock oscillator to a flip-flop’s clock pin is the sum of two latency types:
The delay from the off-chip clock source (PLL output, oscillator) to the clock input port of the chip. This is modelled in STA as a constant delay applied at the clock definition point. It represents board trace delay plus any I/O buffer delay between the oscillator and the chip’s pad.
The delay from the clock input port through the on-chip clock tree (buffers, clock gates, spine drivers) to each flip-flop’s clock pin. This is the dominant component in most designs. Post-CTS, the actual network latency is read from the SPEF parasitics and computed by propagating clock edges through the physical clock tree.
Clock skew is the spatial variation in clock arrival time across different flip-flops on the same clock domain. Two flip-flops nominally clocked at the same frequency may see the clock edge arrive at different times because of different routing path lengths and buffer delays.
| Skew type | Definition | Effect on setup | Effect on hold |
|---|---|---|---|
| Positive (useful) skew | Launch FF clock arrives before capture FF clock | Increases setup margin (data has more time to travel) | Decreases hold margin (data must arrive later) |
| Negative (harmful) skew | Capture FF clock arrives before launch FF clock | Decreases setup margin (effective period is shorter) | Increases hold margin |
| Local skew | Skew between two physically adjacent flip-flops | Critical for timing closure between near cells | Primary cause of hold violations post-CTS |
| Global skew | Maximum skew across the entire clock domain | Used as CTS quality metric; typical target < 50–100ps | Any global skew is a worst-case bound |
Jitter is temporal uncertainty in clock edge arrival. Unlike skew (spatial), jitter varies from cycle to cycle. STA models jitter conservatively as a worst-case window:
The deviation of any single clock cycle from the ideal period. If the nominal period is 1.000 ns, period jitter means any given cycle might be 0.985 ns or 1.015 ns. STA uses the maximum period jitter as part of clock uncertainty. Period jitter always reduces setup margin.
The change in period between two consecutive cycles. Important for PLL-based designs where the VCO frequency may fluctuate. Cycle-to-cycle jitter determines how much the clock period varies over two adjacent cycles — relevant for flip-flops that might capture data one cycle early or late.
The maximum deviation of any clock edge from its ideal position over a long measurement window. Less relevant for digital STA but important for PLL characterisation and spread-spectrum clocking analysis.
Let’s trace CPPR through a specific example. Two flip-flops (FF_L = launch, FF_C = capture) share the first two clock tree buffers (BUF_1 and BUF_2), then diverge (BUF_L feeds FF_L, BUF_C feeds FF_C).
Clock Tree Synthesis (CTS) optimises the clock network to achieve specific targets. These targets directly affect STA results:
| CTS metric | Typical target (28nm) | Effect if violated |
|---|---|---|
| Global skew | < 80 ps (0.08 ns) | Setup margin reduced by skew amount; timing violations across chip |
| Local skew | < 30 ps (0.03 ns) | Hold violations between adjacent flip-flops |
| Insertion delay | 0.3–0.8 ns (depends on die size) | Less impact on timing directly; affects power via clock switching |
| Max transition on CK pins | < 0.15 ns | High slew on clock inputs degrades flip-flop setup/hold window |
| Clock power | 20–40% of total power budget | Thermal issues if clock buffers are over-sized |
| Aspect | Pre-CTS STA | Post-CTS STA |
|---|---|---|
| Clock delays | Ideal (estimated via set_clock_latency) | Propagated (actual tree delays from SPEF) |
| Clock uncertainty | Large (includes estimated skew, 0.15–0.3 ns) | Small (jitter only, 0.05–0.15 ns) |
| Hold violations | Rare (ideal clocks don’t show local skew) | Common (real skew appears; hold closure needed) |
| CPPR | Not applied (ideal clock has no common path) | Essential (removes shared-buffer pessimism) |
| Accuracy | Approximate; used for synthesis guidance | Sign-off quality with correct parasitics |
Pre-CTS ideal clocks do not reflect real clock tree delays. Post-CTS STA with set_propagated_clock is required for valid timing closure because: (1) actual insertion delays may differ from estimates by 10–30%; (2) local skew causing hold violations only appears with real tree delays; (3) CPPR correction is only meaningful with a real common clock path structure.
set_clock_latency -sourceset_propagated_clock; always enable CPPRSource latency is the off-chip delay from the clock oscillator to the chip’s clock input pad (board trace + I/O buffer). Network latency is the on-chip delay from the clock pad through the clock tree buffers to each flip-flop’s clock pin. Pre-CTS, both are modelled with set_clock_latency. Post-CTS, the network latency is computed by propagating the clock edge through the actual routed clock tree.
Skew is the spatial difference in clock arrival time between two flip-flops on the same clock domain. Positive skew (launch FF clock arrives before capture FF) increases setup margin but reduces hold margin. CTS targets minimise global skew (<80ps typical) to avoid both setup violations from harmful skew and hold violations from local skew variations.
Period jitter is the maximum deviation of any single clock period from the ideal period — it bounds how much any one cycle can be short. Cycle-to-cycle jitter is the maximum change between two adjacent periods — how much the clock “wanders” from cycle to cycle. Both are modelled in STA via clock uncertainty. Period jitter directly limits the maximum achievable clock frequency.
If two flip-flops share clock buffers BUF_1 (0.120 ns) and BUF_2 (0.180 ns), OCV with 5% derating makes BUF_1 = 0.126 ns (late for launch) and 0.114 ns (early for capture). CPPR recognises that BUF_1 cannot be simultaneously slow and fast: it removes the 0.012 ns pessimism from that buffer. For BUF_2 it removes another 0.018 ns. Total CPPR recovery = 0.030 ns — slack that would have been wasted without CPPR.
Post-CTS clock uncertainty drops to jitter-only because actual skew is now captured in propagated clock delays. Typical values: setup uncertainty 0.05–0.15 ns (period jitter + margin), hold uncertainty 0.03–0.08 ns. Pre-CTS setup uncertainty was 0.15–0.30 ns because it had to estimate skew. After CTS, update set_clock_uncertainty to the smaller post-CTS values before timing sign-off.