A chip that has passed through place-and-route represents months of optimisation work. When a timing violation, functional bug, or DRC issue is discovered after P&R — especially close to tape-out — re-running the full flow is often too costly in time. Engineering Change Orders (ECOs) are the surgical approach: make the minimum targeted change to the physical implementation to fix the problem, without disturbing everything else.
An ECO is a post-layout change to the gate-level netlist that is implemented in the physical layout by modifying cell placements and metal routing rather than re-running the full P&R synthesis flow. ECOs are used when:
The ECO process uses the existing placed-and-routed database as its starting point, makes targeted changes, and re-routes only the affected nets. The goal is to preserve as much of the original routing as possible to avoid re-running LVS, DRC, and STA from scratch on the entire design.
| ECO type | What changes | Scope | Mask layers affected |
|---|---|---|---|
| Timing ECO | Cell size changes, buffer insertions, Vt swaps — no logic change | Fixing WNS/TNS violations post-sign-off | Metal only (if spare cells used) or full if new cells placed |
| Functional ECO | Logic gates added/removed/replaced; RTL and netlist both updated | Fixing a functional bug found post-P&R | Full (poly + metal) unless metal-only is possible via spare cells |
| Metal-only ECO | Metal routing reconnections only; transistors unchanged | Any fix that can be implemented using pre-placed spare cells | Metal layers only (M1–upper) |
| DRC ECO | Layout geometry changes to fix design rule violations | Post-tapeout preparation or foundry rule updates | Depends on DRC violation location |
Manufacturing a chip requires separate masks for each layer. The base layers (poly, active diffusion, N-well) are the most expensive and have the longest fabrication turnaround time — often 4–6 weeks. Metal layers are cheaper and faster to update — 1–2 weeks.
A metal-only ECO makes changes only to metal connections (M1 and above), leaving the base layers unchanged. This is only possible if the needed logic can be implemented using pre-placed spare cells that already exist on the die at the poly layer. The metal-only ECO re-routes connections to those spare cells to implement the new function.
Spare cells are standard cells (inverters, buffers, AND, OR, NAND, NOR gates) that are placed during initial P&R in a regular grid pattern across the die, even though they have no logic function initially. Their power and ground pins are connected to the power rails, but their inputs are tied to VDD or VSS, making them electrically dormant. Their outputs are left floating.
When a metal-only ECO is needed, the ECO tool selects the nearest available spare cell of the correct type, reconnects its input nets via new metal routing, and connects its output to the required net. The spare cell’s transistors were already in place — only metal mask changes are needed.
After the ECO changes are determined (by PrimeTime or the designer manually), the layout tool performs incremental P&R on only the affected cells and nets:
| Aspect | Metal-Only ECO | Gate ECO (full layer) |
|---|---|---|
| Mask cost | Low (only metal masks) | High (all layers) |
| Fab turnaround | 1–2 weeks | 4–6 weeks |
| Logic flexibility | Limited by spare cell types and locations | Full flexibility; any logic change |
| Timing impact | May be worse (spare cells may be farther from target) | Can optimize placement for minimum delay |
| When to use | Small functional bugs; timing ECOs near tape-out deadline | Large functional changes; when spare cells are insufficient |
| Risk | May not have enough spare cells if many bugs found | Re-running DRC/LVS/STA on entire affected area |
An ECO is not complete until: (1) timing is re-signed-off with the post-ECO SPEF at all corners; (2) DRC is clean in the ECO’d area (and ideally globally); (3) LVS passes with the post-ECO netlist vs post-ECO layout; (4) functional simulation passes on the post-ECO netlist; (5) the ECO change is documented in the design database with revision control. Partial sign-off is never acceptable.
An ECO (Engineering Change Order) is a post-layout modification to fix timing violations, functional bugs, or DRC issues on a placed-and-routed design, without re-running the full synthesis and P&R flow. ECOs are surgical changes that preserve as much of the existing layout as possible to save time and avoid disrupting already-clean sign-off results.
A timing ECO changes only cell strengths or inserts buffers to fix timing — the logic function stays the same. A functional ECO changes the logic itself (add/remove/replace gates) to fix a functional bug and requires RTL modification, re-synthesis, and full re-verification. Functional ECOs are larger in scope and risk; timing ECOs are more contained.
A metal-only ECO makes changes only to the metal routing layers (M1 and above), without modifying the base layers (poly, diffusion) where transistors are defined. By leaving base layers unchanged, only metal masks need to be re-fabricated — 1–2 weeks turnaround instead of 4–6 weeks. This requires pre-placed spare cells to implement the changed logic.
Spare cells are standard logic cells (inverters, NAND, NOR, AND, OR gates) placed during initial P&R with their inputs tied to VDD/GND (making them dormant) and outputs unconnected. During a metal-only ECO, the ECO tool selects the nearest available spare cell of the correct type and reconnects it via new metal routing, activating it to implement the new logic function without touching base layers.
PrimeTime ECO mode reads the post-layout netlist and SPEF parasitics, runs STA to find violations, then runs eco_opt to compute the minimum cell changes needed to fix timing. It generates a change script (write_changes) that can be applied in Innovus or ICC2 for incremental placement and routing, followed by re-extraction and STA verification to confirm the ECO fixed the issue.