STA Sign-off Checklist

Q: What corners must pass STA sign-off?

STA sign-off requires all corners from the MCMM configuration to pass clean: at minimum SS (Slow Slow) process corner at highest temperature and lowest voltage for setup, FF (Fast Fast) at lowest temperature and highest voltage for hold. Most production designs also include TT, SSG (for scan-shift), and worst-case IO corners. All modes (functional, scan, JTAG, test) must pass at all relevant corners.

Q: What is the STA sign-off criteria for WNS and TNS?

For tape-out sign-off, WNS (Worst Negative Slack) must be >= 0.000 ns at every corner and every mode — zero or positive. TNS (Total Negative Slack) must also be 0 at every corner — meaning no path in the design has negative slack. NVP (Number of Violating Paths) must be 0. Any exception to these rules requires written sign-off documentation from the project lead with a clear technical justification and risk assessment.

Q: What is the role of OCV/AOCV/POCV in sign-off?

On-chip variation (OCV) accounts for manufacturing process variability within a single die — identical gates at different locations on the chip may have slightly different delays. At sign-off, timing must pass with OCV derating applied (typically AOCV or POCV at advanced nodes). Sign-off WNS ≥ 0 must be met after applying the OCV derating factors. Without OCV, sign-off would be overly optimistic and silicon might fail.

Q: What must be verified for clock domain crossings at STA sign-off?

STA sign-off requires that all CDC paths are either properly synchronised (through synchronisers verified by CDC tool), constrained as set_false_path (with CDC tool confirmation that the path is truly asynchronous and handled in RTL), or constrained as max_delay with known safe values. No unintentional asynchronous paths between clock domains should exist. A CDC tool (like Meridian CDC or Spyglass CDC) report with zero errors is required alongside STA sign-off.

Q: What documents are required for STA sign-off?

STA sign-off typically requires: (1) timing report summary showing WNS=0 and TNS=0 at all corners/modes; (2) exception documentation listing every set_false_path and set_multicycle_path with justification; (3) CDC tool report showing zero unhandled crossings; (4) OCV/AOCV settings used; (5) corner and mode list with which library files were used at each corner; (6) sign-off checklist signed by lead timing engineer and design lead. Some companies also require a golden netlist checksum.

By EcrioniX · Updated June 2026

STA sign-off is the final gate before tape-out. It is a formal declaration that timing has been fully verified at all corners, in all operating modes, with all physical effects (OCV, crosstalk, clock skew) accounted for — and that every path in the design meets its timing requirement. This page gives you the complete sign-off checklist used in production ASIC design.

1. What STA sign-off means

Sign-off timing is different from implementation timing. Implementation timing uses fast, approximate models to guide P&R decisions. Sign-off timing uses:

Signoff-quality SPEF: full RC extraction at all metal layers (not wireload models)
Signoff Liberty files: characterised at exact PVT corners, with CCS or ECSM models
Propagated clocks: real clock tree insertion delays from CTS, not ideal clocks
OCV/AOCV/POCV derating: applied to account for within-die process variation
Crosstalk delta-delay: SI analysis enabled with extracted coupling capacitances
All MCMM corners and modes: every PVT corner, every operating mode analysed

2. The complete sign-off corner matrix

Analysis	Process corner	Voltage	Temperature	Purpose
Setup (worst)	SS (Slow-Slow)	V_min	T_max (e.g. 125°C)	Slowest logic path — catches setup violations
Setup (nominal)	TT (Typical)	V_nom	25°C	Verifies nominal operation
Hold (worst)	FF (Fast-Fast)	V_max	T_min (e.g. −40°C)	Fastest logic — data arrives earliest, catches hold violations
Leakage (worst)	FF	V_max	T_max	Not timing, but used for power sign-off
Scan shift (setup)	SS	V_min	125°C	Scan clock path setup — often at slower scan clock frequency
Scan capture (hold)	FF	V_max	−40°C	Scan capture hold — DFT-specific

3. The sign-off checklist

Timing criteria: WNS = 0, TNS = 0, NVP = 0 at ALL corners and modes

No exceptions without written documentation and project lead sign-off. Every remaining violation after closure must either be fixed or carry a written technical justification with risk acceptance. Hold violations have zero tolerance — they cannot be deferred.

1
MCMM setup: Run STA at all PVT corners (min SS/TT/FF × temperature range). Confirm WNS ≥ 0 at each setup corner in each mode.
2
MCMM hold: Run STA at all PVT corners for hold analysis. Confirm WNS (min) ≥ 0 at each hold corner in each mode. Zero hold violations — period.
3
Propagated clocks: Verify that all timing runs used propagated clock mode (real CTS insertion delays), not ideal clocks. Check set_propagated_clock [all_clocks] is in the SDC.
4
OCV/AOCV/POCV applied: Confirm derating factors are correct for the foundry node and corner. Check which OCV mode is active with report_ocv_setting.
5
Crosstalk SI analysis enabled: Confirm SI mode is active (set_si_mode -enable_delta_delay true). Check report_si_bottleneck for any delta-delay violations.
6
SPEF from final routing: Parasitics extracted from the final, DRC-clean routing database. Not from pre-route wireload. Check SPEF timestamp matches routing database.
7
CDC exceptions verified: All set_false_path between asynchronous clock domains must be confirmed by CDC tool (Meridian CDC, Spyglass CDC). No unhandled asynchronous crossings.
8
Multicycle path exceptions documented: Every set_multicycle_path has a written justification of the architectural property that guarantees the multi-cycle behaviour. Verified in RTL and gate simulation.
9
All operating modes covered: Functional, scan shift, scan capture, JTAG, low-power (retention), and any other design modes all run and clean.
10
Scan mode setup: Scan-shift paths at the scan clock frequency (typically 10–50 MHz) are clean. Scan capture (at-speed) meets the functional clock frequency if at-speed testing is required.
11
Power domain crossings: For multi-voltage designs, level-shifters and isolation cells are correctly modelled at the appropriate domain voltage. Setup and hold check across domain boundaries passes.
12
No new hold violations from ECO: Verify that any late-stage ECOs (especially buffer insertions for hold) did not introduce new setup violations. Re-run both max and min timing after every ECO.
13
Clock frequency vs target: Achieved frequency (1 / minimum WNS-adjusted period) meets or exceeds the product specification. Document the achieved frequency at each corner.
14
Sign-off library versions locked: Record exact library file names, version numbers, and checksums used at sign-off. These must not change between sign-off and tapeout submission.
15
Sign-off database golden: Tapeout submission uses exactly the same netlist and SPEF files that were used for sign-off. No post-sign-off modifications without re-running sign-off.

4. Sign-off reporting commands

Complete STA sign-off reporting script

## ── Load sign-off environment ── source signoff_setup.tcl ; # sets lib, netlist, SPEF paths for this corner set_propagated_clock [all_clocks] ## ── Enable all physical effects ── set_si_mode -enable_delta_delay true set_ocv_mode -enable_pocv true ; # or set_timing_derate for AOCV ## ── Run timing update ── update_timing -full ## ── Worst-case summary: must all be >= 0 ── report_timing_summary -slack_lesser_than 0.001 \ -max_paths 10 -nworst 5 ## ── Detailed violations (should be ZERO items) ── report_timing -delay_type max -nworst 20 -slack_lesser_than 0 \ -path_type full > setup_violations_report.txt report_timing -delay_type min -nworst 20 -slack_lesser_than 0 \ -path_type full > hold_violations_report.txt ## ── Per-clock-group summary ── foreach clk [get_object_name [all_clocks]] { set wns [get_attribute [get_timing_paths -delay_type max \ -group $clk -nworst 1] slack] puts "Clock $clk : WNS = $wns" } ## ── OCV settings in effect ── report_ocv_setting ## ── SI analysis results ── report_si_bottleneck -delta_delay -significant_power 0.5 ## ── Exception list (must be reviewed/documented) ── report_exceptions > exceptions_list.txt set fp [open exceptions_list.txt r] set n [llength [split [read $fp] "\n"]] close $fp puts "Total exception lines: $n <- review all of these"

5. The sign-off flow step-by-step

6. Common sign-off failures and their causes

Failure	Typical root cause	Resolution
WNS < 0 only at SS corner	A critical path was fixed at TT but still fails SS due to higher delay derating	Size up additional cells; verify OCV factors; check if the path is critical at SS
Hold violations at FF corner	ECO buffers removed or insufficient; CTS skew too high	Insert more delay cells; check hold-aware CTS; verify ECO was applied correctly
Scan capture failures at at-speed	Launch-to-capture scan path too long at the functional clock frequency	Add scan clock buffering; check scan path constraints; consider dedicated scan corners
Cross-domain paths without exception	CDC paths not constrained; new paths added in late ECO not constrained	Run CDC tool; add appropriate set_false_path or set_max_delay; verify in CDC tool
SPEF timestamp mismatch	SPEF extracted from a different DEF revision than the sign-off netlist	Re-extract from the exact same routing database used for tapeout

The golden rule of sign-off

The netlist, SPEF, and SDC used for sign-off must be identical to what is submitted for tapeout. Any change after sign-off — including a “trivial” DRC fix, a spare cell connection, or a clock tree buffer swap — requires re-running sign-off timing. There is no such thing as a change too small to affect timing in a multi-GHz chip at advanced nodes. One re-routed net can shift a nearby victim net’s coupling capacitance enough to cause a crosstalk failure.

Day 15 — Course Finale — Key Takeaways

Sign-off uses real parasitics: signoff-quality SPEF from final routing, not wireload models
All corners and modes: WNS ≥ 0 at every PVT corner (SS, TT, FF) and in every operating mode (functional, scan, JTAG, low-power)
Hold violations: zero tolerance — must be completely fixed before any sign-off approval
OCV + SI both active: signoff without OCV derating and crosstalk is invalid at advanced nodes
Exception audit: every false path and multicycle path must have a written architectural justification
CDC tool required: STA alone cannot verify asynchronous crossings; a dedicated CDC tool report is mandatory
Golden netlist lock: the exact netlist, SPEF, and SDC used at sign-off are frozen and submitted unchanged to tapeout
Any post-sign-off change requires re-sign-off — no exceptions, no matter how small the change seems

Congratulations — You completed the EcrioniX STA Course!

You’ve covered every major topic in Static Timing Analysis: from first principles of setup and hold, through Liberty files, PVT corners, OCV, timing exceptions, crosstalk, clock trees, reading reports, fixing violations, ECO flow, and finally sign-off. You now have the conceptual foundation and practical tool knowledge to work in ASIC timing closure.

Back to STA Course Index

Frequently Asked Questions

What corners must pass STA sign-off?

At minimum: SS (Slow-Slow) at Vmin/Tmax for setup, FF (Fast-Fast) at Vmax/Tmin for hold, and TT at nominal for functional verification. Production designs also include SSG (for scan shift), FSSG, and IO interface corners. Every defined mode at every corner must show WNS ≥ 0 and zero hold violations.

What is the STA sign-off criteria for WNS and TNS?

WNS ≥ 0.000 ns at every corner and every mode. TNS = 0 (no path with negative slack). NVP = 0 (zero violating paths). Any remaining violation requires a formal waiver with written justification, risk assessment, and project lead signature — and even then, hold violations have zero tolerance and cannot be waived.

What is the role of OCV/AOCV/POCV in sign-off?

OCV accounts for manufacturing variation within a single die — identical gates at different locations have slightly different delays. At sign-off, timing must pass after OCV derating is applied to all paths. At advanced nodes (16nm and below), POCV (statistical sigma-based) is the preferred method. Sign-off without OCV is invalid because it ignores a real physical source of timing failure.

What must be verified for clock domain crossings at STA sign-off?

All CDC paths must be either synchronised (verified by CDC tool) or formally constrained as false paths with CDC tool confirmation. A CDC tool report with zero unhandled asynchronous crossings is a mandatory sign-off artifact alongside the timing reports. STA alone cannot detect CDC violations — a dedicated CDC tool is required.

What documents are required for STA sign-off?

Required: (1) timing report showing WNS=0/TNS=0 at all corners/modes; (2) exception list with architectural justification for every FP and MCP; (3) CDC tool report showing zero unhandled crossings; (4) OCV settings confirmation; (5) library version record with checksums; (6) sign-off checklist signed by timing lead and design lead. The golden netlist checksum is also recorded in the sign-off document.