Animate a 6-transistor SRAM cell and a 1T1C DRAM cell side-by-side. Write, read, and hold data. Watch the DRAM capacitor slowly leak charge and trigger a refresh. Understand the physics that shapes every CPU memory hierarchy decision.
Every design decision in the memory hierarchy flows from these fundamental trade-offs.
| Parameter | 🟢 6T SRAM | 🔵 1T1C DRAM |
|---|---|---|
| Cell Construction | 6 MOSFETs (4 in cross-coupled inverters + 2 access transistors) | 1 MOSFET access transistor + 1 storage capacitor (Cs) |
| Silicon Area / Bit | ~50–100 μm² per bit (large) | ~6–8 μm² per bit (ultra-dense) ✓ |
| Access Time | 0.5 – 2 ns (near-instant) ✓ | 30 – 60 ns (sense-amp limited) |
| Refresh Required? | No — static bistable state, holds data as long as power applied ✓ | Yes — capacitor leaks. Must refresh every 32–64 ms |
| Read Operation | Non-destructive — Q and Q̄ nodes are just sensed ✓ | Destructive — reading empties capacitor into bitline; must rewrite immediately |
| Write Operation | Drive BL/BL̄ to forced values, WL HIGH breaks the latch, new state locks in | WL HIGH, drive BL HIGH or LOW to charge or discharge Cs |
| Power (Static) | Near zero when idle (transistors biased off in stable state) | Near zero per cell — but refresh cycles consume dynamic power ✓ |
| Power (Active / Refresh) | Only switching power during access | Continuous refresh overhead (~15–20% of total DRAM power budget) |
| Volatility | Volatile — loses data when power is removed | Volatile — loses data when power removed (or refresh stops) |
| Process Complexity | Standard CMOS process — no special steps needed ✓ | Requires special deep-trench or stacked capacitor fabrication steps |
| Cost per Bit | Very high (6× more area than DRAM) | Very low — most cost-efficient volatile RAM ✓ |
| Typical Density | MBs (kB for L1, MB for L2/L3) | GBs (4–64 GB typical) ✓ |
| Primary Usage | CPU L1/L2/L3 Cache, Registers, TLBs, Branch Predictors, FIFOs | Main System Memory (DDR3/4/5, LPDDR, HBM2, GDDR) |
| Noise Immunity | High — full-swing VDD/GND logic levels ✓ | Low — tiny ΔV on bitline requires careful sense-amplifier design |
SRAM's cross-coupled inverters provide instant, stable logic levels. No sense-amp amplification delay, no refresh overhead, no capacitor physics to fight. A CPU L1 cache access completes in 3–5 clock cycles. Putting DRAM that close to the core would stall the processor 30–100 cycles per access — every instruction would wait.
A 16 GB SRAM system would require 96 billion transistors and occupy dozens of square meters of silicon. DRAM's 1T1C architecture packs 16 GB onto a single ~8 mm² die stack. The 30–60 ns latency is hidden by caches, out-of-order execution, and prefetching — making DRAM the only practical choice for system memory.
The 6T SRAM cell forms a bistable latch using two cross-coupled CMOS inverters: M1/M2 and M3/M4. Two access NMOS transistors M5 and M6 are gated by the Wordline (WL).
HOLD (WL = 0): Access transistors M5 and M6 are OFF. The cross-coupled inverters hold the state indefinitely as long as VDD is supplied. The latch is in a stable equilibrium — Q is pulled to VDD (logic 1) by M3/M4's PMOS path while Q̄ is pulled to GND.
READ (WL = 1): Bitlines BL and BL̄ are precharged to VDD/2. WL goes HIGH, turning on M5 and M6. The cell node Q begins discharging BL (if Q=0) or Q̄ discharges BL̄. The sense amplifier detects the tiny differential voltage (ΔV ≈ 100–200 mV) and amplifies to full rail. This is non-destructive — the cell state is preserved.
WRITE (WL = 1): Drive BL=1 and BL̄=0 for writing logic 1. The external drive strength must overpower the feedback inverter to flip the bistable. WRITE assist techniques (negative WL voltage, BL boosting) help at low VDD.
A DRAM cell stores one bit as the presence or absence of charge on storage capacitor Cs (typically 25–30 fF for modern DRAM). The access NMOS transistor is gated by the Wordline.
WRITE: WL goes HIGH (access transistor ON). BL is driven HIGH (to write '1') or LOW (to write '0'). The capacitor charges or discharges through the transistor to the BL voltage level.
READ (Destructive!): BL is precharged to VDD/2. WL goes HIGH. Cs shares its charge with the bitline capacitance CBL. The resulting ΔV is:
Capacitor Leakage (Retention Time): The sub-threshold leakage of the access transistor slowly discharges Cs even when WL=0. At room temperature, Cs retains data for ~64 ms (worse at elevated temperatures). The DRAM controller must issue a REFRESH command to every row within this window.
Both SRAM and DRAM read operations rely on a differential sense amplifier (cross-coupled inverter pair) to detect tiny voltage differences on the bitlines and amplify them to full VDD/GND levels.
The sense amplifier is enabled after a sufficient ΔV has developed on BL/BL̄ (typically 50–100 mV). It acts as a positive-feedback latch that regeneratively amplifies the difference to full swing in ~1–2 ns. For DRAM, this sense-amp phase dominates the total row access time (tRCD ≈ 13–16 ns in DDR4).
This is why DRAM is slower than SRAM: SRAM's cross-coupled inverters are already the sense amplifier (the internal cell nodes ARE full-swing); DRAM requires an external sense amplifier to resolve a 5% signal from the capacitor.
Modern DRAM is not monolithic. Different applications demand different DRAM packaging and interface optimization:
All these are still 1T1C DRAM cells at the core — the innovations are in the I/O PHY, packaging, and refresh management.
Asked at Intel, Qualcomm, Apple Silicon, NVIDIA, Samsung, Micron, and ARM in hardware engineering interviews.