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Topics Directory

A clean map of every public learning hub on EcrioniX. Paths below are the same URLs you already know — nothing was moved, so old shared links keep working.

Foundations HDL & RTL Timing & Sign-off Protocols Courses Tools & Labs Career

1. Foundations

Start here if you are new to digital design or refreshing basics.

Digital Electronics
Gates, Boolean, flip-flops, FSM, memory
B.Tech ECE
Signals & Systems, Control Systems
General Electronics
Industry context & explainers
Semiconductors
Transistor evolution & fundamentals

2. HDL, RTL & Verification

Write synthesizable RTL and verify it.

Verilog Tutorials
Modules → FSMs → RTL patterns
RTL Design
Coding style, CDC, resets, pipelines
SystemVerilog
SVA, classes, coverage, UVM intro
SV Verification Series
Day-by-day verification curriculum
Verification Hub
UVM, TB, formal, coverage
VLSI Hub
ASIC concepts & building blocks

3. Timing, CDC & Sign-off

Close timing and ship working silicon.

Static Timing Analysis
Setup/hold, SDC, CTS, OCV
Clock Domain Crossing
Metastability, sync, async FIFO
Physical Design
Floorplan → route → sign-off
Logic Synthesis
RTL to gates & constraints
DFT
Scan, ATPG, BIST overview
Low Power
Clock gating, power intent
RTL → Silicon
End-to-end ASIC flow chapters

4. Protocols & Interconnect

On-chip and off-chip buses every designer meets.

Protocols Hub
AXI, APB, AHB, PCIe, DDR, CXL…
Serial Protocols
SPI · I²C · UART
CXL Course
Cache coherent interconnect
Chiplets & UCIe
Die-to-die & packaging

5. Structured Courses

Multi-day paths with a clear order — also listed on the Courses roadmap.

All Courses Roadmap
Visual path for beginners → advanced
FPGA from Scratch
25 lessons · hardware first
RISC-V from Scratch
CPU from ISA to pipeline
ARM Architecture
30-day Cortex deep dive
DFT Course
Scan · ATPG · BIST
RISC-V + Accelerator
AI accel with RISC-V
FPGA Neural Network
Edge AI on FPGA
AI Chip Design
NPU / accelerator concepts
HBM3 Controller
Memory controller project

6. Tools & Interactive Labs

Practice without installing EDA tools.

Tools Hub
All utilities in one place
Verilog Simulator
Run HDL in the browser
CDC Lab
Metastability & sync visualizer
FSM Lab
Moore vs Mealy waveforms
K-Map Solver
Boolean minimization
Logic Gate Simulator
Build circuits visually
Lab Hub
Extra interactive experiments

7. Career & Community

Interview prep, jobs, and getting help.

Interview Prep
VLSI · RTL · PD questions
VLSI Jobs
Roles & hiring landscape
Career Roadmap
How to enter chip design
Claude for VLSI
AI prompts for engineers
About
What EcrioniX is for
Contact
Ask for the next topic
Premium Courses
CDC & RTL masterclass access

Internal linking note: every card above points at an existing public path. Shared links like /verilog/, /sta/, and /rtl_design/ are unchanged. Prefer this Topics page (or hub pages) when you want category browsing; use search on the homepage when you want keyword lookup.