Four deep lab sessions covering the physics every VLSI engineer needs to own — from I-V curves to CMOS inverter VTC to subthreshold leakage. See the equations become live curves.
A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled current source. The gate voltage (Vgs) controls whether a conducting channel forms between source and drain. Below the threshold voltage (Vth) — cutoff, no current. Above Vth, the channel inverts: first behaving like a resistor (triode region), then saturating as Vds increases and the channel pinches off at the drain end. Every simulation in this lab is driven by the same two equations that SPICE uses for first-order modeling.
Family of Id–Vds curves for multiple Vgs values, saturation boundary, operating point
Each colored curve is a constant-Vgs I-V trace. The dashed purple parabola is the saturation boundary — the locus of points where Vds = Vgs − Vth. To its left: triode (resistive). To its right: saturation (current source). The white dot is your operating point.
Channel length modulation (λ): Drag λ above 0 and watch the saturation curves tilt upward. This is finite output resistance ro = 1/(λ·Id). At λ = 0 the curves are perfectly flat — the ideal long-channel model. Real 28 nm transistors have λ ≈ 0.1–0.3 V⁻¹.
Transconductance gm = ∂Id/∂Vgs|Vds = kn(Vgs−Vth): The slope of Id vs Vgs in saturation. Higher W/L → higher gm → more amplification per unit Vgs swing.
// MOSFET drain current — first-order SPICE model
function Id_nmos(Vgs, Vds, Vth, kn, lam) {
if (Vgs < Vth) return 0; // cutoff
const Vov = Vgs - Vth;
if (Vds < Vov) { // triode
return kn * ((Vov * Vds) - (Vds * Vds / 2));
}
return (kn / 2) * Vov * Vov * (1 + lam * Vds); // saturation
}
The gate is separated from the silicon channel by a thin oxide (SiO₂ or HfO₂ in modern nodes). Applying a positive voltage to the NMOS gate attracts electrons to the surface, forming an inversion layer — the channel. The threshold voltage Vth sets the minimum Vgs needed to sustain inversion:
where Vfb is the flatband voltage, φF = (kT/q)·ln(NA/ni) is the Fermi potential, and Qdep is the depletion charge. Process engineers adjust Vth by changing doping (NA), oxide thickness (tox → Cox = εox/tox), or by channel ion implantation — giving the LVT/SVT/HVT variants used in every SoC today.
Short-channel effects (SCE): As L shrinks below ~100 nm, the drain electric field starts to compete with the gate for channel control. This lowers Vth (drain-induced barrier lowering, DIBL) and degrades subthreshold slope. FinFETs and gate-all-around (GAA) transistors wrap the gate around the channel on 3 sides (or all 4) to restore gate control at sub-10 nm nodes.
Vin vs Vout curve, noise margins NMH/NML, switching threshold Vm
The Voltage Transfer Characteristic (VTC) is the DC fingerprint of the inverter. A rail-to-rail VTC (Vout goes all the way to VDD and GND) indicates strong switching. The switching threshold Vm is where Vin = Vout. A symmetric VTC has Vm = VDD/2 — achieved when knWn = kpWp, meaning Wp/Wn ≈ μn/μp ≈ 2–3 for typical processes.
Noise margins: NMH = VOH − VIH, NML = VIL − VOL. These are the maximum noise amplitudes the output can inject into the input of the next gate without causing a logic error. A well-designed inverter has NMH = NML ≈ VDD/2 in the ideal case.
Wp/Wn effect: Drag Wp/Wn left (→1). Vm shifts toward GND — PMOS is weaker, inverter favors pull-down. Drag right (→5). Vm shifts toward VDD. Asymmetric Vm means unequal noise margins and different rise/fall times.
CMOS dominates digital IC design because its static power dissipation is near zero. In steady state, one of PMOS (pull-up) or NMOS (pull-down) is always off, creating no DC path from VDD to GND. Dynamic power P = α·C·VDD²·f dominates — where α is activity factor. This is why VDD scaling (every process node lowers VDD ~15%) is the most effective power-reduction lever in digital design.
The CMOS inverter as the universal cell: Every static CMOS gate (NAND, NOR, complex gate) is a complementary network of PMOS pull-up and NMOS pull-down. The pull-up network is the dual of the pull-down network. For a 2-input NAND: two NMOS in series (pull-down), two PMOS in parallel (pull-up). NMOS in series → effective Wn must be doubled to match the drive current of a single NMOS of width Wn.
Log-scale Id–Vgs, LVT vs SVT vs HVT, subthreshold swing annotation
In the subthreshold regime (Vgs < Vth), the channel current is diffusion-driven and follows an exponential: Id ∝ exp(qVgs/nkT), where n ≥ 1 is the ideality factor. The subthreshold slope SS = n·(kT/q)·ln(10) ≈ 60 mV/decade at 300 K when n = 1 (ideal gate electrostatics, no interface traps).
Real planar MOSFETs have n = 1.1–1.5 due to interface trap density (Dit) and depletion capacitance (Cdep). FinFETs reduce n by wrapping the gate around 3 sides, suppressing Cdep. Gate-all-around (GAA) nanosheets further improve this. This 60 mV/dec limit is why you cannot simply lower VDD without degrading Ion/Ioff — the subthreshold leakage at Vgs = 0 is set by exp(−Vth/SS·ln10), and every 60 mV reduction in Vth multiplies leakage by 10×.
Every modern SoC uses all three Vth flavors simultaneously. A typical distribution: ~15% LVT on the most critical timing arcs (crossing multiple clock domains, datapaths constrained to <50 ps), ~70% SVT for general logic, ~15% HVT in scan chains, clock gating cells, and always-on power domains that need near-zero standby leakage.
Power gating takes this further — a high-Vth power switch (header/footer cell) is inserted between VDD and the logic block. When the block is idle, the switch cuts off supply and leakage drops to junction leakage only (~fA/µm). The state retention registers (backed by always-on supply) save the machine state before power-down and restore after wake-up.
DTCO (Design-Technology Co-Optimization): At 7 nm and below, the Vth split is not simply a designer choice — it's co-optimized with the process team. The foundry tunes implant recipes to hit specific Ion/Ioff windows for each Vth flavor, and the PnR tool performs Vth swapping (LVT→HVT on non-critical cells) during timing closure to meet both speed and leakage targets simultaneously.
W/L vs drive current, gate capacitance, propagation delay, and area
The propagation delay of a gate driving a load Cload with intrinsic capacitance Cint is:
where h = Cload/Cg is the electrical effort and τ₀ is the intrinsic delay. Sizing the gate up (increasing W/L by factor s) scales: Id ∝ s (good), Cg ∝ s (bad — loads previous stage), Cint ∝ s (bad). The minimum path delay for a chain of N gates is achieved when each stage has equal logical effort — the result is the "equal-h" condition.
The optimal W/L for a standalone inverter driving FO stages of identical size is W/L = √(FO) — for FO4 (the standard benchmark load), W/L ≈ 2× minimum. That's why standard cell libraries ship cells at 1×, 2×, 4×, 8× drive strengths — they are pre-sized for common fan-outs.
| Parameter | 180 nm | 28 nm | 7 nm | 3 nm |
|---|---|---|---|---|
| Gate length Lg | 180 nm | 28 nm | ~6 nm eff. | ~3 nm eff. |
| Transistor type | Bulk CMOS | Bulk / FD-SOI | FinFET | GAA Nanosheet |
| VDD (typical) | 1.8 V | 0.9 V | 0.7 V | 0.65 V |
| Vth (SVT) | ~0.5 V | ~0.4 V | ~0.3 V | ~0.25 V |
| Subthreshold slope | 80–100 mV/dec | 70–80 mV/dec | 62–68 mV/dec | ~62 mV/dec |
| Ion/Ioff | ~10⁵ | ~10⁶ | ~10⁷ | ~10⁷–10⁸ |
| Cox (MΩ/m²) | ~8 | ~30 | ~60 | ~80 |
| Foundry example | TSMC 0.18µm | TSMC N28 | TSMC N7 | TSMC N3E |
DIBL (Drain-Induced Barrier Lowering): At short L, the drain depletion region merges with the source depletion, lowering the potential barrier at the source. This reduces Vth as Vds increases — DIBL = −ΔVth/ΔVds, typically 30–100 mV/V for 28 nm planar.
Velocity saturation: At high electric fields (short L), carrier velocity saturates at vsat ≈ 10⁷ cm/s for electrons. The square-law Id ∝ (Vgs−Vth)² becomes linear: Id ≈ Cox·W·vsat·(Vgs−Vth). This is why the simple long-channel equations overestimate current at short L.
FinFET solution: By making the silicon body a tall, narrow fin (~5–8 nm wide at 7 nm node) and wrapping the gate around 3 sides, the gate capacitance overwhelms the drain depletion capacitance. DIBL drops to <20 mV/V, SS approaches 62 mV/dec, and short-channel control is restored — allowing continued scaling without catastrophic leakage.
GAA (Gate-All-Around) at 3 nm: Nanosheets (horizontal silicon ribbons, 4–6 stacked) surrounded by gate on all 4 sides. Even better electrostatic control than FinFET. Allows independent width tuning per sheet for performance vs. power optimization within a single standard cell.