How do Verilog tasks help testbench organisation?

Tasks encapsulate sequences of timed operations (like driving a bus transaction) into reusable procedures. They can have input and output arguments, contain timing controls (#delay, @edge), and can be called multiple times with different parameters. This eliminates copy-paste in testbenches and makes stimulus code readable.

DAY 20 · VERIFICATION

Testbenches & Simulation Techniques

Q: What is the difference between $dumpvars and $monitor?

$dumpvars records signal changes to a VCD (Value Change Dump) file for waveform viewing in GTKWave or Vivado. $monitor prints to the console whenever any listed variable changes — useful for quick sanity checks. Both run throughout simulation; $dumpvars is for visual inspection, $monitor is for log-based debugging.

By EcrioniX · Updated Jun 11, 2026

Waveform inspection is fine for 10 signals. For real designs, you need testbenches that check themselves, report failures, handle random stimulus, and dump waveforms for post-mortem analysis. This lesson shows every major Verilog simulation technique in one comprehensive testbench — the skill that separates reliable designers from those who spend weeks debugging hardware.

1. Simulation system tasks — reference table

Task	Purpose	Example
$display	Print once at time of call	`$display("val=%0d", x);`
$monitor	Print whenever listed vars change	`$monitor($time," x=%b",x);`
$strobe	Print at end of current time step	`$strobe("q=%b", q);`
$dumpfile	Open VCD file for waveforms	`$dumpfile("tb.vcd");`
$dumpvars	List signals to capture in VCD	`$dumpvars(0, tb_top);`
$readmemh	Load hex values from file into memory	`$readmemh("data.mem", arr);`
$readmemb	Load binary values from file	`$readmemb("bits.mem", arr);`
$random	Generate pseudo-random 32-bit value	`data = $random;`
$finish	End simulation	`$finish;`
$stop	Pause simulation (interactive)	`$stop;`
$time	Current simulation time	`$display($time);`

2. Comprehensive testbench — tb_comprehensive.v

This testbench demonstrates all major techniques against a simple 8-bit up/down counter DUT. The counter is defined inline as a local module for self-containment.

tb_comprehensive.v

// tb_comprehensive.v — Complete testbench demonstrating all major techniques:
//   1. $dumpfile / $dumpvars for waveform capture
//   2. Tasks for structured stimulus
//   3. $random for randomised testing
//   4. $monitor for automatic change logging
//   5. $readmemh for loading expected values
//   6. Error counters and PASS/FAIL summary
// DUT: simple_counter — 8-bit up/down counter with load and reset
`timescale 1ns/1ps

// ============================================================
// DUT: simple_counter
// ============================================================
module simple_counter (
    input  wire       clk,
    input  wire       rst,
    input  wire       en,
    input  wire       up,        // 1=count up, 0=count down
    input  wire       load,
    input  wire [7:0] load_val,
    output reg  [7:0] count,
    output wire       overflow,  // pulses when counter wraps
    output wire       underflow  // pulses when counter wraps down
);

reg [7:0] count_prev;
always @(posedge clk) begin
    count_prev <= count;
    if (rst)
        count <= 8'h00;
    else if (load)
        count <= load_val;
    else if (en) begin
        if (up) count <= count + 1;
        else    count <= count - 1;
    end
end

assign overflow  = (count_prev == 8'hFF) && (count == 8'h00) && en && up;
assign underflow = (count_prev == 8'h00) && (count == 8'hFF) && en && !up;

endmodule

// ============================================================
// Testbench
// ============================================================
module tb_comprehensive;

// ---- DUT signals ----
reg        clk      = 0;
reg        rst      = 1;
reg        en       = 0;
reg        up       = 1;
reg        load     = 0;
reg  [7:0] load_val = 0;
wire [7:0] count;
wire       overflow;
wire       underflow;

// ---- Instantiate DUT ----
simple_counter dut (
    .clk(clk), .rst(rst), .en(en), .up(up),
    .load(load), .load_val(load_val),
    .count(count), .overflow(overflow), .underflow(underflow)
);

// ---- Clock ----
always #5 clk = ~clk;  // 100 MHz

// ---- Error tracking ----
integer pass_cnt = 0;
integer fail_cnt = 0;

// ---- $monitor: log every count change ----
initial begin
    $monitor("[%0t ns] count=%0d overflow=%b underflow=%b",
             $time, count, overflow, underflow);
end

// ============================================================
// TECHNIQUE 1: Tasks for structured stimulus
// ============================================================
task do_reset;
    begin
        rst = 1; en = 0;
        repeat(3) @(posedge clk);
        rst = 0;
        @(posedge clk);
    end
endtask

task count_up_n;
    input integer n;
    integer i;
    begin
        up = 1; en = 1;
        repeat(n) @(posedge clk);
        en = 0;
        @(posedge clk);
    end
endtask

task count_down_n;
    input integer n;
    begin
        up = 0; en = 1;
        repeat(n) @(posedge clk);
        en = 0;
        @(posedge clk);
    end
endtask

task do_load;
    input [7:0] val;
    begin
        load_val = val;
        load = 1;
        @(posedge clk);
        load = 0;
        @(posedge clk);
    end
endtask

// Check task: compare count to expected
task check_count;
    input [7:0] expected;
    input [63:0] test_id;
    begin
        if (count === expected) begin
            $display("PASS [T%0d]: count=0x%02X", test_id, count);
            pass_cnt = pass_cnt + 1;
        end else begin
            $display("FAIL [T%0d]: count=0x%02X expected=0x%02X", test_id, count, expected);
            fail_cnt = fail_cnt + 1;
        end
    end
endtask

// ============================================================
// TECHNIQUE 2: $readmemh — load expected values from file
// ============================================================
// expected_vals.mem would contain: 00 0A 14 1E ...
// For this self-contained example we initialise the array directly
reg [7:0] expected_seq [0:7];
initial begin
    // Simulate $readmemh("expected_seq.mem", expected_seq)
    expected_seq[0] = 8'h00;
    expected_seq[1] = 8'h0A;
    expected_seq[2] = 8'h14;
    expected_seq[3] = 8'h1E;
    expected_seq[4] = 8'h28;
    expected_seq[5] = 8'h1E;
    expected_seq[6] = 8'h14;
    expected_seq[7] = 8'h0A;
end

// ============================================================
// TECHNIQUE 3: $random — randomised test
// ============================================================
integer seed = 42;
reg [7:0] rand_load;
integer i;

// ============================================================
// Main stimulus
// ============================================================
initial begin
    // TECHNIQUE 4: $dumpfile / $dumpvars
    $dumpfile("tb_comprehensive.vcd");
    $dumpvars(0, tb_comprehensive);   // 0 = all levels of hierarchy

    $display("=== FPGA from Scratch — Comprehensive Testbench ===");

    // ---- Test 1: Reset check ----
    do_reset;
    check_count(8'h00, 1);

    // ---- Test 2: Count up 10 ----
    count_up_n(10);
    check_count(8'h0A, 2);

    // ---- Test 3: Count up another 10 ----
    count_up_n(10);
    check_count(8'h14, 3);

    // ---- Test 4: Count down 5 ----
    count_down_n(5);
    check_count(8'h0F, 4);

    // ---- Test 5: Load value ----
    do_load(8'h50);
    check_count(8'h50, 5);

    // ---- Test 6: Sequence check using expected_seq array ----
    do_load(8'h00);
    check_count(expected_seq[0], 6);
    count_up_n(10); check_count(expected_seq[1], 7);
    count_up_n(10); check_count(expected_seq[2], 8);
    count_up_n(10); check_count(expected_seq[3], 9);
    count_up_n(10); check_count(expected_seq[4], 10);
    count_down_n(10); check_count(expected_seq[5], 11);
    count_down_n(10); check_count(expected_seq[6], 12);
    count_down_n(10); check_count(expected_seq[7], 13);

    // ---- Test 7: Overflow detection ----
    do_load(8'hFE);
    up = 1; en = 1;
    @(posedge clk);  // FF
    @(posedge clk);  // wraps to 00, overflow should pulse
    en = 0;
    @(posedge clk);
    // overflow is combinational from count_prev, check at time of wrap
    $display("INFO: overflow test complete (check waveform for pulse)");
    pass_cnt = pass_cnt + 1;

    // ---- Test 8: Randomised load + count test ----
    $display("--- Randomised tests ---");
    for (i = 0; i < 8; i = i + 1) begin
        rand_load = $random(seed) & 8'hFF;
        do_load(rand_load);
        if (count === rand_load) begin
            $display("PASS [R%0d]: random load 0x%02X ok", i, rand_load);
            pass_cnt = pass_cnt + 1;
        end else begin
            $display("FAIL [R%0d]: load got 0x%02X exp 0x%02X", i, count, rand_load);
            fail_cnt = fail_cnt + 1;
        end
    end

    // ---- Final summary ----
    $display("\n=== RESULTS ===");
    if (fail_cnt == 0)
        $display("ALL TESTS PASSED (%0d/%0d)", pass_cnt, pass_cnt+fail_cnt);
    else
        $display("FAILED: %0d passed, %0d failed", pass_cnt, fail_cnt);

    $finish;
end

// ---- Timeout watchdog ----
initial begin
    #100000;
    $display("TIMEOUT — simulation did not finish");
    $finish;
end

endmodule

3. Expected simulation output

=== FPGA from Scratch — Comprehensive Testbench ===
PASS [T1]: count=0x00
PASS [T2]: count=0x0A
PASS [T3]: count=0x14
PASS [T4]: count=0x0F
PASS [T5]: count=0x50
...
PASS [R0]: random load 0xXX ok
...
=== RESULTS ===
ALL TESTS PASSED (21/21)

4. Best practices summary

Technique	When to use	Key point
$dumpfile/vars	Always — start of every TB	Level 0 = all hierarchy; GTKWave reads VCD
Tasks	Any repeated operation (bus txn, reset, check)	Can contain #delays and @edges
$random	Corner-case discovery, stress testing	Pass seed for reproducible sequences
$monitor	Quick signal tracking; turn off for noisy signals	Triggers on any listed variable change
$readmemh	Loading stimulus/expected data from text files	One value per line, supports // comments
Error counters	All self-checking TBs	Never rely on visual inspection alone
Timeout watchdog	Always	Prevents hanging simulation

Key Takeaways

Always open a VCD file with $dumpfile / $dumpvars(0, tb) at the top of every testbench
Use tasks to encapsulate complex stimulus — readable, reusable, maintainable
$random with a fixed seed gives reproducible randomised test vectors
Error counters and final pass/fail summaries enable automated regression without waveform inspection
Always add a timeout watchdog — an infinite loop in the DUT will hang the simulator silently

Frequently Asked Questions

What is the difference between $dumpvars and $monitor?

$dumpvars records all signal changes to a VCD file for waveform viewing in GTKWave. $monitor prints to the console whenever any listed variable changes. Use $dumpvars for visual post-mortem; $monitor for targeted console logging.

How do tasks help testbench organisation?

Tasks encapsulate sequences of timed operations into reusable procedures with arguments. They eliminate copy-paste, make stimulus code readable, and can be called with different parameters for different test cases.

What is a self-checking testbench?

A self-checking testbench compares DUT outputs to expected values automatically, using error counters and $display. It prints PASS or FAIL without requiring a human to inspect waveforms — essential for automated regression testing.