Top 22 Physical Design Interview Questions

Both types represent voltage degradation across the on-chip Power Distribution Network (PDN), but have completely different physical root causes:

• Static IR Drop ($V_{drop} = I_{avg} \times R$): Caused by the total average current flowing through finite metal resistance. High in data-center blocks with heavy static leakage. Remedies: Increase power ring/strap widths, increase via density at strap intersections, and reduce mesh pitch.
• Dynamic IR Drop ($V_{drop} = L \frac{di}{dt} + I_{peak} R$): Occurs within 100-200 picoseconds following an active clock edge when thousands of flip-flops switch simultaneously. Causes clock jitter, setup timing failures, and functional glitches. Remedies: Insert Decoupling Capacitor (Decap) cells near high-switching clusters to act as local charge reservoirs; stagger clock arrival times; downsize non-critical launch drivers.

Macro placement directly dictates routability, congestion, and timing closure for the entire chip:

• Periphery Placement: Place hard macros along the core boundaries (chip periphery) with pins facing inward toward the standard cell core area to preserve a contiguous, open center for standard cell placement.
• Flyline & Dataflow Alignment: Group macros by interconnect connectivity. If Macro A communicates directly with Macro B, keep them adjacent. If macros communicate with I/O pads, align them near corresponding chip edge pins.
• Channel Width Calculation: Ensure spacing between adjacent macros is calculated based on pin density:
  Channel Width ≥ (Total Pin Count × Pitch) / Available Metal Layers
• Halos (Keepout Margins): A halo is a placement blockage surrounding a macro boundary that prevents standard cells from being placed too close, avoiding pin congestion and protecting power connections.
• Routing Blockages: Used over macro regions to prevent global routers from using lower metal layers that are already consumed by internal memory routing.

Physical implementation relies on non-logical standard cells to satisfy semiconductor DRC and electrical stability:

• Well Tap Cells: Connect N-well to VDD and P-substrate to VSS. In tapless standard cell libraries, they prevent CMOS latch-up by keeping substrate resistance low. Inserted in a regular checkerboard pattern (maximum tap distance specified in DRC, e.g., every 20-30 µm).
• Endcap (Boundary) Cells: Placed at the ends of standard cell rows and around macro boundaries to maintain well continuity and optical proximity correction (OPC) uniformity at row edges.
• Decap Cells (Decoupling Capacitors): Gate oxide capacitors connected between VDD and VSS. Placed near switching hotspots to filter high-frequency noise and resolve dynamic IR drop.
• Tie-High / Tie-Low Cells: Unused standard cell input pins must never be tied directly to VDD/VSS rails (to avoid ESD/EOS damage during power transients). Tie cells provide safe clamped logical 1 or 0 voltages through an internal resistor/transistor.
• Filler Cells: Inserted after detailed routing to fill empty row spaces, ensuring continuous N-well/P-well diffusion and satisfying metal density DRC rules.

Routing congestion occurs when routing demand exceeds available routing tracks in a Global Routing Cell (GCell):

• Identify Root Cause: Is it Pin Density Congestion (too many complex standard cells packed together), Macro Channel Congestion (narrow corridors between macros), or Data-path Multiplexer logic?
• Placement Density Screens: Set partial placement blockages (e.g., 60-70% max density) in congested areas to spread cells apart.
• Cell Padding: Apply keepout halos or cell padding to high-pin-count cells (such as flip-flops with scan and async pins or wide multiplexers) to increase available wire space.
• Reroute Non-Critical Signals: Move non-critical global buses to higher, less congested metal layers.
• Floorplan Expansion: If core utilization is above 75-80% and routing channels are fully saturated, the die size or aspect ratio must be adjusted.

Clock distribution consumes 30-40% of total dynamic chip power. The primary goals of CTS are minimum clock skew, controlled insertion delay (latency), fast and uniform clock transition (slew), and maximum power efficiency.

• Clock Latency (Insertion Delay): The time taken by a clock signal to propagate from the clock definition source (PLL/oscillator) to the clock pin of a flip-flop.
• Clock Skew ($T_{skew} = T_{capture} - T_{launch}$): The difference in arrival times of the clock signal at two interacting flip-flops. Positive skew assists setup timing; negative skew assists hold timing.
• Clock Jitter: Temporal variation in the clock period cycle-to-cycle, caused by PLL thermal noise, power supply ripple, and cross-coupling. Unlike skew (which is spatial), jitter is time-varying and cannot be balanced away by CTS buffers.

Useful skew is the intentional delay or advancement of a clock tree branch to borrow slack from adjacent timing paths:

• Fixing Setup Violations (Positive Skew): If Path A (Launch $\to$ Capture 1) fails setup by 50 ps, but Path B (Capture 1 $\to$ Capture 2) has 200 ps of positive slack, the CTS engine delays the clock arrival at Capture 1 by 60 ps. This steals 60 ps from Path B to satisfy Path A.
• The Critical Trade-Off: Delaying the clock at Capture 1 directly deteriorates the Hold margin on Path A ($T_{launch} + T_{comb} \ge T_{capture} + T_{hold}$). If useful skew is applied too aggressively, hold violations explode.

The Antenna Effect is a manufacturing reliability hazard that occurs during plasma etching of metal layers:

• Physical Mechanism: Long interconnect tracks act as capacitive collectors for charged ions in the plasma chamber. If a long metal wire connects to a thin MOSFET gate oxide without being connected to a diffusion (source/drain) junction, charges accumulate until the dielectric breakdown voltage is exceeded, puncturing the gate oxide permanently.
• Antenna Ratio: Foundries define the maximum allowable ratio:
  Antenna Ratio = (Exposed Metal Area) / (Connected Gate Oxide Area)
• Solution 1: Antenna Diode Insertion: Place a reverse-biased diode connected to the victim net near the gate input pin. The diode provides a safe, low-impedance discharge path to substrate/ground during fabrication.
• Solution 2: Layer Hopping (Jumper Insertion): Route the wire up to a higher metal layer immediately before the gate and drop back down through vias. During lower-layer etching, the long wire is physically disconnected from the gate oxide.

Electromigration is the physical migration of metal atoms caused by the momentum transfer from high-density flowing electrons ("electron wind"). Over years of operation, it causes metal voids (open circuits) and hillocks/whiskers (short circuits to adjacent lines).

Governed by Black's Equation for Mean Time to Failure (MTTF):

MTTF = A · J^(-n) · exp(Ea / (k · T))

Where $J$ is current density ($I/Area$), $T$ is absolute temperature, and $E_a$ is activation energy.

• Signal EM Fixes: Widen metal wires, downsize overpowered drivers, insert multi-cut via arrays, and avoid high output transition slew.
• Power EM Fixes: Add parallel power straps, reinforce via ladders from top metal layers to standard cell rails, and limit max current density per unit width according to foundry design rules.

As process geometries shrink into 7nm, 5nm, and 3nm nodes, manufacturing process variations (doping fluctuations, channel length variations, metal thickness) require sophisticated statistical modeling:

• Traditional OCV (On-Chip Variation): Applies a single flat percentage derate (e.g., +12% on launch path, -10% on capture path). Highly pessimistic because it assumes every single gate in a 30-stage chain is simultaneously at the absolute worst-case corner.
• AOCV (Advanced OCV): Utilizes 2D look-up tables based on logic depth and bounding-box spatial distance. In longer logic chains, statistical variations cancel out (the law of large numbers), allowing lower derate penalties.
• POCV (Parametric OCV): Replaces static derates with statistical normal Gaussian distributions ($\mu \pm n\sigma$). Each cell delay is modeled as nominal delay plus variation sensitive to global and local random factors. Eliminates excessive pessimism and prevents over-buffering, saving 15-20% die area and leakage power.

1. Setup Time Check (Max Delay constraint):

T_launch_clk + T_ck2q_max + T_comb_max ≤ T_period + T_capture_clk - T_setup - T_jitter

Slack Setup = (T_period + T_capture_clk - T_setup - T_jitter) - (T_launch_clk + T_ck2q_max + T_comb_max)

2. Hold Time Check (Min Delay constraint):

T_launch_clk + T_ck2q_min + T_comb_min ≥ T_capture_clk + T_hold + T_margin

Slack Hold = (T_launch_clk + T_ck2q_min + T_comb_min) - (T_capture_clk + T_hold)

Even though an asynchronous reset can be asserted at any time, its de-assertion must never coincide with an active clock edge, or flip-flops will enter metastability:

• Recovery Time (Analogous to Setup): The minimum time an asynchronous control signal (like reset) must remain stable and inactive before the rising edge of the clock.
• Removal Time (Analogous to Hold): The minimum time an asynchronous signal must remain asserted after the active clock edge before it is allowed to release.
• Hardware Solution: An Async Reset Synchronizer (two back-to-back flip-flops with reset tied to the asynchronous pin) ensures the de-assertion of reset is cleanly synchronized to the clock domain.

In deep sub-micron nodes, lateral coupling capacitance between adjacent wires ($C_c$) exceeds substrate ground capacitance ($C_g$).

• Crosstalk Glitch: Occurs when an Aggressor net switches while the Victim net is steady at 0 or 1. If coupling capacitance is high, it injects a voltage spike. If the spike exceeds the receiver's switching threshold and occurs during a latching clock window, it creates a false functional state.
• Crosstalk Delay (Push-out & Pull-in):
  • Opposite-Direction Switching: Effective capacitance doubles due to Miller effect ($C_{eff} = 2 C_c$), causing significant delay push-out (Setup violation).
  • Same-Direction Switching: Effective capacitance drops to near zero ($C_{eff} = 0$), causing delay pull-in (Hold violation).
• Fixes: Double spacing (spacing reduces $C_c$ quadratically), shield critical clock nets with VDD/VSS tracks, upsize the victim driver, or insert repeaters to lower loop impedance.

In modern mobile SoCs with dynamic voltage and power gating domains:

• Level Shifter: Bridges signals crossing between different voltage domains (e.g., 0.65V core domain to 1.1V memory domain). Up-shifters prevent static crowbar leakage in higher-voltage receivers. Down-shifters protect thin-oxide gates from overvoltage breakdown.
• Isolation Cell (ISO): Placed at outputs of a power-gated domain that feeds an always-on domain. When the domain powers down, its outputs float to unknown intermediate voltages (X). The ISO cell clamps the output to a safe known state (0 or 1) using an enable signal.
• Retention Flip-Flop (RFF): Contains a secondary shadow latch connected to an always-on power rail. Before the core power switches off, internal register states are saved into the shadow latch, enabling instant wake-up without full system reboot.

Modern standard cell libraries provide functionally identical footprints with different threshold voltages ($V_{th}$):

• ULVT / LVT (Low Vt): Thin barrier / high doping $\to$ high drive current ($I_{on}$), fastest switching speed, but exponentially higher sub-threshold leakage power. Used exclusively on critical setup timing paths.
• SVT (Standard Vt): Balanced speed and leakage. Used for general logic.
• HVT (High Vt): Higher threshold voltage $\to$ lowest leakage current, but slower switching speed. Ideal for non-critical paths with large positive setup slack.
• Optimization Methodology: Run initial placement and routing with SVT/HVT. Post-CTS and post-route, selectively swap non-critical cells to HVT (reclaiming leakage power) while swapping only failing setup paths to LVT/ULVT.

Physical verification guarantees that the layout can be manufactured and functions identically to the schematic:

• DRC (Design Rule Checking): Geometric checks ensuring metal widths, spacing, enclosure, density, and via rules adhere to foundry process limits. DRC errors cause manufacturing shorts/opens or optical defects.
• LVS (Layout Versus Schematic): Extracts devices (MOSFETs, diodes, capacitors) and electrical nets from polygon layouts and checks one-to-one equivalence with the synthesized gate-level netlist.
• Debugging an LVS Short: Two distinct electrical nets are physically connected. Use layout debugging tools (e.g., Calibre RVE) to highlight the shorted polygon across metal layers. Look for missing pin text labels, overlapping macro ports, or faulty filler cells.
• Debugging an LVS Open: A net in the schematic has no complete physical route in layout. Look for missing vias between metal layers or severed tracks during ECO changes.

When automated optimization stalls, follow this systematic debugging hierarchy:

1. Analyze Timing Report: Inspect the critical path. Is delay dominated by cell delay (logic depth) or net delay (long interconnect / high parasitics)?
2. Check Slew / Transition Violations: If transition times are degraded (>200 ps), buffer the net or upsize the driving cell. Slew degradation causes massive downstream gate delays.
3. Check High Fanout Nets: Replicate driving cells or insert buffer trees to distribute capacitive loading.
4. Multi-Vt Swapping: Swap SVT/HVT cells along the critical path to LVT or ULVT.
5. Relocate Placed Cells: Check layout view. If driver and load are physically placed across opposite corners of the block, create placement bounds or pull them closer manually.
6. Reroute to Higher Metals: Long routes on lower, high-resistance metal layers (M2/M3) should be reassigned to thick, low-resistance top metal layers (M6/M7).

Standard 193nm immersion lithography cannot print features tighter than ~80nm pitch due to optical diffraction limits:

• Double Patterning (LELE - Litho-Etch-Litho-Etch): Polygons on the same metal layer are decomposed into two separate photo-masks, designated as Mask A ("Color 1") and Mask B ("Color 2"). Adjacent parallel lines alternate colors.
• Color Conflict Error: If three wire segments form an odd-cycle loop (like a triangle or tight U-shape) where all three are spaced below the single-mask pitch limit, it is impossible to alternate two colors without two identical colors touching.
• Fixes: Move one segment to another metal layer, re-space the polygon, or introduce a cut mask to break the conflicting loop.

An Engineering Change Order (ECO) modifies a design late in the tapeout cycle without re-running the entire physical design flow:

• Pre-Mask ECO: Performed before mask generation. All base layers (wells, diffusion, poly) and metal layers can be altered freely. Cells can be moved and new standard cells inserted.
• Post-Mask (Metal-Only) ECO: Occurs after silicon wafer fabrication has begun. Base silicon masks (which cost millions of dollars) cannot be changed! Changes are restricted strictly to upper metal interconnect layers.
• Role of Spare Cells: During initial floorplanning, uncommitted Spare Cells (mix of AND, OR, NAND, MUX, DFFs with inputs tied to VSS) are peppered throughout standard cell rows. In a metal-only ECO, the router connects these pre-existing silicon spare cells using metal masks to implement the required logic fix at a fraction of the mask respin cost.

Routing a design with 50 million wires directly at the polygon level is computationally impossible. Routers split the task into three progressive abstractions:

1. Global Routing (GR): The die is partitioned into a coarse 3D grid of Global Cells (GCells). The global router assigns net connections to GCell boundaries without specifying exact geometric coordinates, balancing congestion across layers.
2. Track Assignment (TA): Replaces global routing lines with actual straight wire tracks within each GCell. It attempts to assign long tracks to continuous lines, minimizing via counts.
3. Detailed Routing (DR): Operates on small local SBoxes (Search Boxes). It connects standard cell pins directly to track assignments while adhering strictly to all nanometer design rules (DRC, enclosure, min-area, spacing).

Using a simple 2-input AND gate with an Enable signal directly on a clock wire causes hazardous clock glitches:

• The Problem: If the Enable signal transitions from 0 to 1 while the input clock is HIGH, the AND gate output experiences an immediate rising edge—producing an illegal runt pulse (glitch) that violates flip-flop setup/hold times.
• The Solution: Integrated Clock Gating (ICG) Cell: Combines a negative-level sensitive latch followed by an AND gate. The Enable signal is captured while the clock is LOW and held stable during the clock HIGH phase. This ensures that the gated clock output cleanly transitions only at legitimate clock edges without glitches.

This is one of the most common real-world interview debugging questions. The divergence between post-CTS and post-route timing is typically caused by four factors:

• 1. Parasitic Estimation Discrepancy: Pre-route engines rely on Manhattan or virtual Steiner tree approximations. Post-route extraction uses real geometric wires with real cross-coupling capacitance ($C_c$). If congestion was high, the detailed router created detour wires, doubling net resistance.
• 2. Crosstalk Delay Push-out: Real post-route timing calculates signal integrity (SI) with switching aggressors. Unshielded parallel buses experience heavy Miller capacitance push-out.
• 3. Real Clock Tree Delays vs Virtual Clock: If CTS latency was unpropagated or clock transition degraded across dense routing layers, capture clocks arrived earlier than expected.
• Systematic Remediation Plan:
  1. Generate congestion heatmaps to check if detours occurred in narrow channels.
  2. Enable SI-aware timing analysis in the router to force automatic spacing and shielding.
  3. Run global route optimization (ECO route) to re-order tracks.
  4. Selectively upsize drivers and perform multi-Vt LVT swaps on real critical paths.