The first step of physical design. Aspect ratio, core utilization, macro placement, power delivery planning, I/O ring design, and production floorplan strategy for VLSI chips.
Die planning is the first critical step in physical design. It determines the chip's overall dimensions, aspect ratio, placement zones, and power distribution strategy before any detailed layout begins. Every later step — placement, CTS, routing, timing closure — inherits the consequences of these early decisions.
Key decisions made during die planning:
Die size and aspect ratio (square vs rectangular)
Macro placement (memories, hardmacros, analog blocks)
Core area utilization target (70–80% typical)
Power delivery network (PDN) strategy
I/O ring and pad placement
Routing resource allocation
Clock distribution regions
Why It Matters Most
Poor die planning is the single most expensive mistake in physical design. A weak floorplan can doom timing closure ten steps later — and by then, fixing it means restarting the entire flow. Experienced PD engineers spend weeks on the floorplan because it constrains everything downstream.
2. Aspect Ratio Selection
Aspect Ratio = Die Width / Die Height. It affects routing congestion, macro fit, and I/O perimeter cost. The right choice depends on your macro shapes, package, and dominant routing direction.
Core utilization = (standard cell area + macro area) / available core area. It's the single most important floorplan knob — too low wastes silicon, too high makes timing closure impossible.
Technology Node
Target Utilization
Routing Congestion
Timing Risk
28nm+
60–65%
Low
Low
14nm
70–75%
Moderate
Moderate
7nm
75–80%
High
High
5nm
80–85%
Very High
Very High
Why not 100% utilization?
Routing needs space (metal layers, vias between cells)
Timing optimization needs whitespace (room to move and upsize cells)
Power distribution needs tracks (metal resources for straps)
Higher utilization → exponentially harder to close timing
4. Macro Placement Strategy
Macros are pre-designed blocks: memories (SRAM), hardmacros (PLL, analog), and embedded processors. Their placement is locked early because they're large and immovable once the floorplan is frozen.
Floorplan with Macro Placement (Top-Down)
Placement principles: co-locate SRAMs near the logic that uses them (minimize wire delay), group memories hierarchically (L1 near CPU, L2/L3 toward periphery), place power-hungry macros symmetrically for even heat spread, and route data buses directly from macro to core.
5. Power Delivery Network (PDN) Planning
The PDN delivers power from package pads to every transistor. A poorly planned PDN causes voltage droop (IR drop), timing violations, functional failures, and electromigration. It's planned hierarchically from coarse (package) to fine (cell).
PDN Hierarchy — VDD Distribution
Package
Bulk capacitors on PCB (100µF) — low-frequency response, 1–2 mΩ
Local power rails per cell — ultra-high frequency, 1–3 mΩ
PDN Impedance Budget:
Max allowable voltage drop = 10% of supply
For a 1.8V supply → max 180mV drop
Impedance targets:
Package: 1–2 mΩ (bulk power)
Die: 2–5 mΩ (distribution)
Cell: 1–3 mΩ (local)
Total: < 10 mΩ (ensures < 180mV @ 18A peak)
Design rule: power straps every 100–200µm,
ground return in parallel to minimize loop inductance.
6. I/O Ring & Pad Placement
The I/O ring is the physical boundary holding all pads — power, ground, data, and control. Pad planning balances signal count against power/ground integrity.
Pad ring area: ~1–2% of die area (hundreds of pads)
Power pads: frequent spacing (every 4–8 data pads)
Ground pads: equal or greater than power (return path)
Data pads: grouped by function (control, address, data)
Bump placement: for flip-chip BGA packages (area array)
Pad Type (256-pin example)
Count
Purpose
Power (VDD)
50
Supply current delivery
Ground (GND)
50
Return path, noise reference
Signal (I/O)
100
Data, address, control
Spare
56
Future use / redundancy
7. Core Region Allocation
The core region is the area available for standard cells. A realistic 100 mm² die allocates area across many competing needs: