IR drop analysis, decoupling capacitors, power strap design, electromigration, and PDN simulation — the complete guide to delivering stable power across a VLSI chip.
The PDN delivers stable power from package to every gate on the chip. It spans multiple physical levels, each handling a different frequency range of the current demand. Poor PDN design causes voltage droop, timing violations, and outright functional failures.
PDN Hierarchy — Power Path & Frequency Domains
Package (PCB)
Bulk caps 100µF + ceramic 10–100µF — dominates at DC–100kHz
↓ BGA balls
Die (on-chip)
On-die decap 1–10µF + integrated regulators — dominates at kHz–MHz
↓ Power metal straps
Cell (local)
Local power rails 0.1–1µm wide — dominates at MHz–GHz
2. IR Drop Analysis
IR drop is simply Ohm's law applied to the power grid: voltage lost equals current times resistance. It has two components — static (DC) and dynamic (transient).
Static IR Drop (DC):
V_drop = I_peak × R_path
I_peak = peak current (A)
R_path = resistance from pad to gate (Ω)
Dynamic IR Drop (di/dt droop):
V_droop = L × di/dt
L = inductance of power path (nH)
di/dt = rate of current change (A/ns)
Budget (10% of supply, 1.8V rail → 180mV total):
Static component: 100–120mV
Dynamic component: 60–80mV
Worked example (5nm chip):
Peak current: 50A (all cores active)
R_path: 5mΩ
V_static = 50A × 5mΩ = 250mV ✗ EXCEEDS budget!
Fix: reduce R_path to 3.6mΩ (more straps) OR add decap
Voltage droop waveform during a workload current spike:
Supply Voltage vs Time — Droop on Current Spike
3. Decoupling Capacitors
On-die capacitors store local charge to supply sudden current spikes faster than the package can respond — flattening the droop you saw above. Different cap types cover different frequency bands.
Type
Capacitance
ESR (mΩ)
Frequency Response
Integration
Bulk caps (PCB)
100–470 µF
5–15
1–100 kHz
External
Ceramic caps (PCB)
1–100 µF
2–10
100 kHz–10 MHz
External
On-die MIM caps
1–10 nF
0.5–2
10 MHz–1 GHz
Metal-insulator-metal
Interleaved caps
0.1–1 nF
0.1–0.5
100 MHz–10 GHz
Between metal layers
Placement rule: put decaps near the power consumers (CPU cores, memory macros). Dense clustering improves high-frequency response where it matters most.
4. Power Strap Design
Power straps are wide metal lines that carry power from pads across the die. They form a grid — VDD and GND interleaved — to deliver uniform voltage everywhere.
Power Strap Grid (Top-Down) — Interleaved VDD/GND
Straps every 100µm, 2µm wide on top metals (M8/M9 are thickest, lowest resistance). Resistance: M9 ≈ 3 mΩ/mm, M8 ≈ 5 mΩ/mm. GND straps run perpendicular to VDD for uniform grid coverage and minimal loop inductance.
Power Strap Grid Design (7nm worked example):
Die: 50mm × 50mm, utilization 75%, peak 100A, target IR drop 150mV
Strap width: 2µm (M8), pitch: 100µm, height: 800nm
Resistance per strap: ~1 mΩ/mm
# of straps: 50mm / 100µm = 500 straps
Current per strap: 100A / 500 = 0.2A (well within EM limit)
Result: uniform voltage with < 100mV local variation
5. Electromigration (EM)
Electromigration is metal failure from high current density. Flowing electrons physically push metal atoms over time, creating voids (opens) or hillocks (shorts). It's a latent reliability killer — chips can pass test and fail months later.
Black's Equation (EM lifetime):
MTTF = A × J^(-2) × exp(Ea / kT)
J = current density (A/cm²)
A = process/metal constant
Ea = activation energy (~0.5–0.7 eV for copper)
k = Boltzmann constant
T = absolute temperature (K)
Worked example (5nm, copper):
J_max design rule: 1 MA/cm²
Strap 1µm wide × 0.8µm thick → area = 0.8 µm² = 0.8e-8 cm²
Max current = 1 MA/cm² × 0.8e-8 cm² = 0.8A per strap
For 100A peak: need 100 / 0.8 = 125 straps minimum
Our 500-strap design → SAFE (4× margin)
Note: MTTF ∝ J^-2, so doubling current density cuts lifetime 4×.
EM accelerates sharply with temperature (exp term).
EM is Temperature-Sensitive
Because of the exp(Ea/kT) term, a hotspot running 20°C hotter than its neighbors can fail years sooner. This is why thermal-aware placement (Day 8) and EM sign-off (Day 9) go hand in hand — current density limits must be checked at the worst-case junction temperature.
6. PDN Simulation
PDN analysis uses SPICE-class simulation to predict voltage droop over time before the chip is built. The PDN is modeled as a network of resistors, inductors, and capacitors driven by a realistic current waveform.
Simulation Inputs
Simulation Outputs
Current waveform (from switching activity)
Voltage waveform at critical nodes
PDN model (R, L, C network)
Peak voltage droop vs budget
Voltage regulator (VRM) model
Impedance vs frequency plot
Package + die geometry
Current distribution across straps
Production-grade PDN sign-off also includes:
Temperature variation (EM accelerates at higher temp)
Process variation (metal resistance varies ±10%)
Aging effects (capacitor degradation over lifetime)
7. Real-World PDN Examples
Mobile Processor (Apple A17)
Supply voltage: 0.8–1.3V (dynamic voltage scaling)
Peak current: ~80A (all cores + GPU)
IR drop budget: ~80mV (6% of 1.3V supply)
On-die capacitance: large MIM array near hot blocks
PDN impedance: <2 mΩ @ 1MHz
Server Processor (AMD EPYC)
Supply voltage: 0.6–1.2V (aggressive scaling)
Peak current: ~200A per chiplet
Multiple voltage domains (cores, cache, uncore)
On-die voltage regulators (per-core LDO)
PDN impedance target: <1 mΩ @ 1MHz (very tight)
PDN Design Checklist
✅ Set voltage budget: 10% of supply voltage
✅ Split static vs dynamic: ~70% static, ~30% dynamic
✅ Size power straps: based on current, EM rules, target impedance
✅ Design power grid: uniform spacing, multiple layers, GND return
✅ Add decoupling caps: distributed near power consumers