What is the difference between global and detailed placement?

Global placement coarsely positions all cells to minimize total wire length using quadratic optimization or analytical solvers — the result may have overlaps and isn't legal. Detailed placement then snaps cells to legal rows/sites, removes overlaps, and fine-tunes positions for timing. Global placement takes seconds-minutes; detailed placement takes minutes-hours.

What is routing congestion in placement?

Congestion is when the routing demand in a region exceeds the available routing tracks (supply). It's measured per G-cell tile as demand/supply ratio. High-congestion 'red zones' make routing fail or force long detours that break timing. Placement tools predict congestion early and spread cells to relieve hotspots before routing begins.

What is timing-driven placement?

Timing-driven placement prioritizes timing-critical paths by placing the cells on those paths physically close together, minimizing interconnect delay. It uses net weights derived from timing slack — critical nets get higher weight so the placer keeps them short, even at the cost of slightly longer non-critical nets.

Standard Cell Placement

Global vs detailed placement, congestion analysis, timing-driven placement, power-aware strategies, and production verification — positioning millions of cells for timing and routability.

1. Placement Fundamentals

Placement decides the physical location of every standard cell (logic gate) in the core. It runs after floorplanning and CTS prep, and it directly determines whether the chip can be routed and whether it will meet timing. A good placement minimizes wire length, congestion, and power all at once.

Placement objectives:

Minimize total wire length (reduces both power and delay)
Reduce congestion (avoid routing bottlenecks)
Meet timing constraints (close critical paths)
Optimize power distribution (minimize IR drop hotspots)
Support manufacturability (avoid density hotspots)

2. Placement Algorithms

Global Placement

Coarse positioning of all cells using quadratic / analytical optimization.

Time: seconds to minutes
Output: rough positions (may overlap, not legal)
Goal: minimize global wire length

Detailed Placement

Snaps cells to legal rows/sites, removes overlaps, fine-tunes for timing.

Time: minutes to hours
Output: legal placement (no overlaps)
Goal: legalize + local timing optimization

3. Congestion Analysis

Congestion predicts routing difficulty before routing runs. The placer divides the die into G-cell tiles and compares routing demand against supply in each tile. Where demand exceeds supply, routing will fail or detour — breaking timing.

Congestion Metrics: Overall density = (cell area + routing area) / total area < 70% → plenty of routing space > 80% → tight, hard to close Local (per G-cell tile): overflow = routing_demand − routing_supply overflow > 0 → red zone (must fix) overflow < 0 → blue zone (spare capacity) Common hotspot causes: - Large macros surrounded by many connections - Core logic clustered too tightly - Poor macro placement forcing long detours

Congestion heatmap (top-down die view):

Congestion Heatmap — Routing Demand vs Supply

Fix strategy: move logic away from red zones, reduce local density, and add buffers in blue zones to distribute signal loads.

4. Timing-Driven Placement

Move the cells on critical paths physically closer together so their interconnect is shorter and faster. The placer derives net weights from timing slack — critical nets are kept short even if non-critical nets stretch a little.

Critical-path clustering: cells on the same tight path placed adjacent
Slew-driven placement: reduce interconnect capacitance on timing nets
Buffer insertion: add buffers on long timing wires to meet slew/delay

5. Power-Aware Placement

Concern	Placement Action	Benefit
Thermal hotspots	Spread power-hungry blocks apart	Even heat distribution
Leakage power	Group cells by voltage domain (multi-VDD)	Enables power gating
Switching power	Minimize interconnect length	Less capacitive switching energy
IR drop	Avoid clustering high-current cells	Flatter voltage profile

6. Real-World Placement Examples

7nm Processor

100 mm² die, 75% utilization, ~50M standard cells
Global placement: ~2 minutes
Detailed placement: ~30 minutes
Timing closure: ~95% of paths met after placement

5nm GPU

500 mm² die, 80% utilization (aggressive), 500M+ cells
Hierarchical placement (sub-blocks placed first)
Timing harder: tight skew budget, high power density

Placement Checklist

✅ Define placement constraints: critical paths, thermal limits, keep-outs
✅ Run global placement: reasonable initial wire-length-optimized positions
✅ Analyze congestion: identify red-zone hotspots early
✅ Timing-driven detailed placement: optimize critical paths
✅ Power analysis: check thermal and IR-drop distribution
✅ DFM awareness: avoid density hotspots
✅ Verify legality: no overlaps, all cells in legal sites
✅ Incremental placement: post-route optimization if needed

Next — Day 5: Routing & timing closure — metal layers, via strategy, timing path fixing, DRC, and LVS verification.

← Previous

Day 3: Clock Tree Synthesis

Day 5: Routing & Timing Closure