What is the difference between global and detailed routing?

Global routing assigns each net to a coarse path and metal layers on an abstracted grid, checking that routing is feasible without congestion — it takes seconds to minutes. Detailed routing then draws the actual metal shapes and vias on real layers, obeying all DRC rules — it takes hours to days for large designs.

Why do chips use so many metal layers?

Modern chips use 10-15 metal layers because billions of connections cannot fit on a few layers. Lower layers (M1-M3) are thin with tight pitch for local cell connections; upper layers (M7-M10+) are thick with wide pitch for low-resistance global routing and power distribution. Each layer routes in a preferred direction (alternating horizontal/vertical).

How is a setup timing violation fixed during routing?

Setup violations (data arrives too late) are fixed by: widening wires to reduce RC delay, upsizing driver cells, inserting buffers on long nets, restructuring logic to reduce depth, or adjusting clock skew (useful skew). Tools try these in order of least disruption, re-running timing analysis after each change.

Physical Design Day 5 — Routing & Timing Closure

1. Metal Layers & Via Strategy

Routing uses a stack of metal layers (M1 through M10+ on advanced nodes), each with a specific role. Lower layers are thin and tightly pitched for local connections; upper layers are thick and wide for low-resistance global routing and power.

Layer	Use	Pitch	Resistance
M1	Local interconnect, cell pins	20–40nm	High (thin)
M2–M6	Local / regional routing	40–100nm	Medium
M7–M9	Global routing, power distribution	200–500nm	Low (thick)
M10+	Top metal, bumps, power	500–1000nm	Very low

Metal Stack — Cross Section (thin local → thick global)

Via strategy: use larger vias on lower layers (area-efficient), and double/redundant vias on critical and power nets for reliability.

2. Global vs Detailed Routing

Global Routing

Coarse path + layer assignment on an abstracted grid.

Checks feasibility (no impossible congestion)
Time: seconds to minutes

Detailed Routing

Draws actual metal + vias on real layers.

Obeys all DRC rules, sizes wires for timing
Time: hours to days

3. Timing Closure Techniques

Timing closure ensures every path meets setup and hold. Routing adds real wire RC, so paths that passed on estimates may now fail — and the router/optimizer must fix them.

Timing checks: Setup: data_arrival + clock_skew < clock_period − setup_time Hold: data_arrival − clock_skew > hold_time Common fixes (least → most disruptive): 1. Wire sizing (widen wire → lower R → less delay) 2. Cell upsizing (stronger driver → less delay) 3. Buffer insertion (split long nets) 4. Logic restructuring (reduce path depth) 5. Useful skew (adjust clock arrival — careful with hold)

Worked example — critical path at 10GHz (100ps period):

Critical Path Timing Analysis

Path delay = FF1(20) + AND(15) + OR(12) + MUX(18) + wires(5+4+6+3) = 83ps Setup check: 83 + skew(5) ≤ period(100) − setup(10) 88 ≤ 90 ✓ PASS (2ps slack) If it failed by 5ps, fix options: Option 1 — widen wires: −5ps wire delay → 78ps ✓ Option 2 — upsize MUX: 18→12ps → 77ps ✓ Option 3 — insert buffer on critical path (enables shorter routes)

4. Congestion-Driven Routing

When routing demand exceeds supply, the router iterates to resolve bottlenecks.

Rip-up and reroute: remove routes in congested areas, reroute through less-congested paths
Placement adjustment: nudge cells to reduce demand on hot tiles
Buffer insertion: add buffers in spare (blue) areas to break long nets

5. Design Rule Checks (DRC)

DRC verifies the routed layout obeys the foundry's manufacturing rules. A single violation can make the chip unmanufacturable.

Rule	Typical Value (5nm)	Why It Matters
Minimum spacing	20–30nm	Lithography resolution (no bridging)
Minimum line width	20nm	Minimum reliable feature size
Via array rules	Via spacing	Resistance, yield
Metal density	20–80% window	CMP polishing uniformity
Antenna rules	Gate-area ratio	Gate oxide damage during etch

Common DRC violations and fixes:

DRC Violation Examples (Metal Layer)

❌ Spacing too tight

Fix: increase spacing to ≥20nm (shifts downstream routing)

❌ Via density too low

Fix: add dummy/redundant vias → improves CMP & reliability

DRC tools: Cadence Assura/PVS, Synopsys IC Validator, Siemens Calibre. A 7nm design can start with 10,000s–100,000s of violations — all must reach zero before tape-out.

6. LVS — Layout vs Schematic

LVS confirms the routed layout electrically matches the intended netlist.

Extracts connectivity from the layout (metal + via connectivity)
Compares against the reference netlist (what the logic should be)
Reports shorts, opens, and missing/extra connections

DRC + LVS = Physical Sign-off Gate

DRC asks "can this be manufactured?" and LVS asks "does it implement the right circuit?" Both must be 100% clean before tape-out. We cover the full DRC/LVS deep-dive — antenna rules, PEX, ERC — in Day 6.

7. Real-World Routing Examples

7nm Mobile Chip

~100M nets (signal connections)
Global routing: ~1 hour
Detailed routing: ~24 hours
DRC iterations: 3–5 (typical)
Timing closure: ~98% of paths met

5nm Processor

1B+ nets (massive routing problem)
Hierarchical routing (route by sub-block)
Timing harder: tight skew budgets
Multiple DRC iterations (very tight design rules)

Routing Checklist

✅ Global routing feasibility: no routing-impossible regions
✅ Layer assignment: right metal layers per signal importance
✅ Via strategy: minimize area, double vias on critical/power nets
✅ Timing closure: meet setup/hold with sizing & buffering
✅ Congestion resolution: rip-up/reroute until overflow = 0
✅ DRC verification: all spacing/width/density rules met
✅ LVS verification: layout matches netlist electrically
✅ Signal integrity: check crosstalk and slew violations
✅ Power/ground: verify PDN adequacy after routing
✅ Final sign-off: clean DRC + LVS, ready for next stage

Next — Day 6: DRC & LVS Verification in depth — spacing/enclosure/antenna rules, PEX extraction, ERC, and the iterative DRC closure flow.

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Day 6: DRC & LVS Verification