Yield optimization, CMP metal fill, redundant via insertion, OPC, SRAF, lithography-friendly routing, double patterning, and production DFM strategies for advanced VLSI nodes.
Yield = fraction of chips per wafer that work correctly. At advanced nodes, yield is never 100% — random defects from particles, lithography imperfections, and process variation kill some percentage of every wafer. DFM techniques push yield higher, directly translating to revenue.
Yield Model (Seeds-of-Defect):
Y = e^(-D₀ × A)
D₀ = defect density (defects/cm²) — foundry process parameter
A = die area (cm²)
Example: 5nm TSMC, D₀ = 0.09/cm², die = 100mm² = 1cm²
Y = e^(-0.09 × 1) = e^(-0.09) = 91.4%
DFM improves effective D₀ by reducing sensitivity to defects:
Without DFM: D₀_eff = 0.15 → Y = 86%
With DFM: D₀_eff = 0.09 → Y = 91.4%
Improvement: +5.4 percentage points = ~$10M/month revenue gain
2. CMP Metal Fill
Chemical Mechanical Planarization (CMP) polishes wafer surfaces flat. Without uniform metal density, high-density areas polish slower (hills) and low-density areas polish faster (dishing). Both cause focus problems in subsequent lithography steps, increasing defects.
CMP Planarization — Density Effect
Metal Fill Requirements (TSMC N5):
Target density window: 60–80% per 10×10µm tile
Min density: 60% (prevent dishing)
Max density: 80% (prevent hills, meet spacing rules)
Fill insertion strategy:
1. Measure density per tile after routing
2. Identify tiles below 60% → insert fill shapes
3. Identify tiles above 80% → slot existing metal or skip fill
4. Fill shapes: minimum size = 2× minimum width rule
5. Fill-to-signal spacing: maintain minimum spacing rule
Fill power impact:
Dummy fill adds capacitance to nearby signal nets
Typical capacitance increase: 2–5% per layer
Fill must be excluded from timing-critical net neighborhoods
EDA tools automatically set exclusion zones around critical wires
3. Redundant Via Insertion
A single via has a small but nonzero failure probability (~0.01% per million vias at 5nm). With billions of vias on a modern chip, that means thousands of potential failure points. Redundant vias (2×1 or 2×2 arrays) drastically reduce this risk.
Single Via vs Redundant Via
Single Via (Risky)
Redundant Via 2×1 (Safe)
Both vias must fail simultaneously for the net to open. Independent failure probability: 0.01% × 0.01% = 0.000001% — 10,000× improvement.
Redundant Via Insertion Strategy:
Priority order:
1. Power/ground vias: ALWAYS use 2×2 arrays (4 vias)
2. Clock nets: ALWAYS use 2×1 arrays (2 vias)
3. Timing-critical signals: use 2×1 where space allows
4. Non-critical signals: best-effort (fill where spacing permits)
Coverage targets (industry standard):
Power/ground: 100% redundant
Clock: 95%+ redundant
Critical signal: 80%+ redundant
Total average: 60–70% redundant
Area overhead: ~5–10% routing area increase
Worth it: a single via open failure can kill the entire chip!
4. Optical Proximity Correction (OPC)
At sub-wavelength lithography (features smaller than the light wavelength), diffraction causes printed shapes to differ from the mask shapes. OPC pre-distorts the mask so that the wafer-printed result matches the intended design.
OPC — Mask Correction for Diffraction
Intended Shape
Perfect rectangle in design
Without OPC (printed)
Corners rounded, line ends pull back
With OPC (mask)
Serifs added → prints like target
5. Sub-Resolution Assist Features (SRAF)
SRAFs are tiny mask features smaller than the resolution limit — they don't print on the wafer, but they improve the aerial image contrast of the main features around them, reducing line-width variation.
Technique
Purpose
When Applied
Node
OPC (Optical Proximity Correction)
Pre-distort mask to compensate diffraction
All features, especially corners
180nm+
SRAF / Scattering Bars
Improve contrast of isolated lines
Isolated lines and spaces
90nm+
Source Mask Optimization (SMO)
Co-optimize illumination and mask shape
Critical layers
28nm+
Inverse Lithography Technology (ILT)
Compute optimal mask from target pattern
Full-chip critical layers
7nm+
EUV + OPC
13.5nm wavelength enables direct patterning
Critical layers at 5nm and below
5nm–1nm
6. Double Patterning (SADP/LELE)
At 14nm and below, a single exposure cannot pattern features at minimum pitch. Double patterning splits one layer into two exposures:
LELE Double Patterning (Litho-Etch-Litho-Etch)
Mask 1
Odd lines
+
Mask 2
Even lines
=
Result
Half-pitch!
Key DFM constraint: Lines from different masks (different colors) cannot connect on the same layer. EDA tools perform coloring — assigning each wire to mask 1 or mask 2 — and flag coloring conflicts where topology makes this impossible.
7. Lithography-Friendly Design Rules
Preferred routing directions: Horizontal on M2, Vertical on M3 (reduces forbidden pitch violations)
Avoid acute angles: 45° bends cause diffraction hotspots → use 90° bends only on lower metals
Line-end spacing: Line ends need extra spacing (tip-to-tip) vs parallel wire spacing
Avoid T-junctions at minimum pitch: Creates lithography hotspots — add jog to offset T-junction
Wire width uniformity: Avoid wide wires next to minimum-width wires (CMP dishing)
Via land area: Extend metal beyond minimum enclosure on timing-critical vias (redundancy and reliability)
8. DFM Tools
Tool
Vendor
DFM Function
Calibre YieldAnalyzer
Siemens
Yield prediction, critical area analysis
IC Validator DFM
Synopsys
DFM rule checks integrated with ICC2
Voltus-Fi
Cadence
Fill insertion with timing awareness
Mentor Calibre OPC
Siemens
OPC generation and verification
Synopsys Proteus
Synopsys
ILT and SMO mask optimization
DFM Production Checklist
✅ Metal fill inserted: All layers within 60–80% density window
✅ Fill excluded from critical nets: Timing-critical wire neighborhoods kept fill-free
✅ Redundant vias on power: 100% of VDD/GND vias are 2×2 arrays
✅ Redundant vias on clock: ≥95% of clock vias are redundant
✅ Coloring complete: Double-patterning layers fully colored, no conflicts