What is Cadence Innovus used for?

Cadence Innovus is an industry-leading place-and-route (PnR) EDA tool for digital IC physical design. It handles floorplanning, power planning, cell placement, clock tree synthesis (CTS), routing, and timing/DRC sign-off. Innovus uses Tcl scripting for automation and integrates with Tempus STA and Quantus PEX for full sign-off.

What is the difference between Innovus and ICC2?

Both are leading PnR tools: Cadence Innovus is known for excellent ECO capabilities, strong multi-corner timing optimization, and tight Tempus STA integration. Synopsys ICC2 (IC Compiler II) is known for superior routing quality, Zroute hierarchical router, and tight PrimeTime/StarRC integration. Both are used at leading semiconductor companies; tool choice often depends on existing EDA ecosystem.

How do you learn Cadence Innovus?

The best path: (1) Install Cadence Innovus (university or company license), (2) Learn Tcl scripting basics — all Innovus commands are Tcl, (3) Run a small RISC-V core or AES block through the full flow, (4) Study the Innovus User Guide for each major step: init_design, place_design, ccopt_design, route_design, (5) Practice with OpenROAD (open-source) which has similar Tcl command structure.

Physical Design Day 13 — EDA Tools: Cadence Innovus & Synopsys ICC2

1. The EDA Tool Landscape

Two tools dominate production physical design: Cadence Innovus and Synopsys IC Compiler II (ICC2). Both handle the complete RTL-to-GDSII flow — floorplanning through routing — with different strengths. Most large design houses use both, choosing per project.

Cadence Innovus

✅ Best-in-class ECO closure
✅ Excellent multi-corner timing opt
✅ Native Tempus STA integration
✅ Strong clock concurrent opt (ccopt)
✅ Quantus PEX for fast extraction
⚠️ Routing QoR slightly behind ICC2

Synopsys ICC2

✅ Best routing QoR (Zroute engine)
✅ Superior for advanced nodes (3nm)
✅ Native StarRC PEX integration
✅ PrimeTime sign-off integration
✅ Strong multi-patterning support
⚠️ ECO flow less seamless than Innovus

2. Innovus Complete Flow — Tcl Script

The full Innovus flow from netlist to GDSII is driven by Tcl commands. In production, engineers write automation scripts that run the entire flow in batch mode overnight.

##############################################
# innovus_flow.tcl — Complete PnR Flow Script
# Usage: innovus -batch -source innovus_flow.tcl
##############################################

# 1. Initialize Design
init_design
read_netlist  netlist/top.v
read_libs     -liberty pdk/timing/tt0p8v25c.lib
read_lef      pdk/lef/tech.lef pdk/lef/cells.lef

# 2. Load Constraints
read_sdc  constraints/top.sdc
set_analysis_mode -analysisType onChipVariation -cppr both

# 3. Floorplan
floorPlan -site CoreSite -r 1.0 0.75 5 5 5 5
# -r aspect_ratio utilization left bottom right top margins

# 4. Power Planning
add_rings -nets {VDD GND} -width 10 -spacing 5 -layer {M9 M8}
add_stripes -nets {VDD GND} -width 2 -spacing 0.5 \
            -layer M8 -direction horizontal -set_to_set_distance 100
sroute -connect corePin -layerChangeRange {M1 M2}

# 5. Placement
place_design
refine_placement -effort high
check_floorplan

# 6. Clock Tree Synthesis (CTS)
create_clock_tree_spec -out_file cts.spec
ccopt_design
set_propagated_clock [all_clocks]

# 7. Post-CTS Optimization
optDesign -postCTS -hold -setup -effort high

# 8. Routing
routeDesign -globalDetail
# Verify routing
verify_drc   -report reports/drc.rpt
verify_connectivity -report reports/conn.rpt

# 9. Post-Route Optimization
optDesign -postRoute -setup -hold -effort high
optDesign -postRoute -drv

# 10. Filler Cells
add_fillers -cell FILL32 FILL16 FILL8 FILL4 FILL2 FILL1 \
            -prefix FILLER

# 11. Metal Fill (DFM)
addMetalFill -layer {M2 M3 M4 M5} -minDensity 0.6 -maxDensity 0.8

# 12. Sign-off Checks
report_timing -max_paths 100 -path_type full > reports/timing.rpt
report_power  > reports/power.rpt
report_area   > reports/area.rpt

# 13. GDSII Export
streamOut top.gds -mapFile pdk/map/gds_map.txt -libName top \
          -units 1000 -mode ALL

puts "Flow complete. Check reports/ for sign-off results."

3. Key Innovus Commands Reference

Stage	Command	Purpose
Init	`init_design`	Load design from config file (innovus.tcl)
Init	`read_netlist`	Load gate-level Verilog netlist
Floorplan	`floorPlan`	Set die area, core margins, utilization
Power	`add_rings`	Add power ring around core
Power	`add_stripes`	Add power straps across die
Placement	`place_design`	Global + detailed placement
CTS	`ccopt_design`	Concurrent clock and timing optimization
Routing	`routeDesign`	Global + detailed routing
Optimization	`optDesign`	Timing/DRV optimization (pre/post-CTS/route)
Verification	`verify_drc`	DRC check (native Innovus rules)
Export	`streamOut`	Export GDSII for tape-out

4. ICC2 Flow — Tcl Script

##############################################
# icc2_flow.tcl — Synopsys ICC2 PnR Flow
# Usage: icc2_shell -f icc2_flow.tcl
##############################################

# 1. Create Library and Design
create_lib -technology pdk/tech.tf \
           -ref_libs {pdk/cells.ndm} top.dlib
read_verilog  netlist/top.v
link_block

# 2. Load Timing and Constraints
read_parasitic_tech_file pdk/tluplus/typical.tluplus
read_sdc  constraints/top.sdc

# 3. Floorplan
initialize_floorplan -target_utilization 0.75 \
                     -core_offset {5 5 5 5}

# 4. Power Plan
create_pg_ring_pattern ring_pattern \
    -layers {{M9 -width 10 -spacing 5} {M8 -width 10 -spacing 5}}
set_pg_strategy ring -pattern ring_pattern -nets {VDD GND}
compile_pg -strategies ring

# 5. Placement
place_opt
# Clock-aware global placement
clock_opt -from build_clock -to route_clock

# 6. Post-CTS Optimization
place_opt -from final_place -to final_opto

# 7. Routing
route_auto -max_detail_route_iterations 10
route_opt

# 8. Verification
verify_lvs
verify_drc -results_db drc.db

# 9. Chip Finish
add_tap_cell_array -lib_cell TAPCELL -distance 50
insert_stdcell_filler -cell_name {FILL32 FILL8 FILL1}

# 10. Write GDSII
write_gds -output top.gds -merge_files pdk/gds/cells.gds

puts "ICC2 flow complete."

5. Timing Optimization Commands Deep-Dive

### Innovus Timing Optimization — Detailed Commands

# Check timing at each stage
report_timing -late  -max_paths 20 -path_type full  ;# setup check
report_timing -early -max_paths 20 -path_type full  ;# hold check

# Pre-CTS optimization (setup only)
optDesign -preCTS -setup -effort high -addInstancePrefix preOpt_

# Post-CTS optimization (setup + hold)
optDesign -postCTS -setup -hold -effort high

# Post-route optimization — fix DRV (design rule violations)
optDesign -postRoute -drv              ;# fix max cap/tran violations
optDesign -postRoute -setup -effort high  ;# close remaining setup
optDesign -postRoute -hold  -effort high  ;# close hold violations

# ECO timing fix (after initial sign-off attempt)
setEcoMode -refinePlace true -addFill true -allowCellMovement true
ecoDesign -setupViolation -holdViolation

# Check results
report_timing_summary   ;# shows WNS, TNS per corner
report_constraint       ;# shows all constraint violations

6. Tool Comparison — When to Use Which

Criterion	Cadence Innovus	Synopsys ICC2
Routing QoR	Good	Best (Zroute)
ECO flow	Best (native ECO)	Good
CTS quality	Excellent (ccopt)	Excellent (clock_opt)
STA integration	Tempus (native)	PrimeTime (external)
PEX integration	Quantus	StarRC
Multi-patterning	Good	Best
Script language	Tcl	Tcl
Market share (2025)	~48%	~45%
Best for	ECO-heavy designs, mobile SoC	Advanced nodes, server chips

7. OpenROAD — Open-Source Alternative

OpenROAD is the leading open-source PnR tool, developed under the DARPA IDEA program. It uses the same Tcl command structure as Innovus and is excellent for learning and university projects.

### OpenROAD flow (open-source, same Tcl structure)
# Available free at: https://github.com/The-OpenROAD-Project

read_lef  pdk/sky130/sky130_fd_sc_hd.tlef
read_lef  pdk/sky130/sky130_fd_sc_hd_merged.lef
read_liberty pdk/sky130/sky130_fd_sc_hd__tt_025C_1v80.lib
read_verilog netlist/top.v
link_design top

read_sdc constraints/top.sdc

initialize_floorplan -utilization 45 -aspect_ratio 1.0 \
                     -core_space 10

place_pins -hor_layers metal3 -ver_layers metal2

global_placement -density 0.5
detailed_placement

clock_tree_synthesis -root_buf CLKBUF_X3 -buf_list CLKBUF_X3

route_design
write_def   top_routed.def
write_gds   top.gds
puts "OpenROAD flow done — free, open-source PnR!"

EDA Tool Flow Checklist

✅ Tcl flow script written: All steps automated, reproducible batch run
✅ Constraints loaded (SDC): Clock definitions, I/O delays, false paths
✅ Library versions locked: Correct PVT corner libs for each run
✅ Placement constraints applied: Fixed macros, keep-out zones
✅ ccopt/clock_opt complete: CTS meets skew and latency targets
✅ Route DRC clean: Zero DRC violations after routing
✅ Timing sign-off complete: All MCMM corners pass in tool
✅ GDSII exported: Correct layer map, merged with PDK cells
✅ Reports archived: Timing, power, area, DRC reports saved

Next — Day 14: Physical Design Sign-off and Tape-out — the complete sign-off checklist, GDSII package for foundry, PDK version locking, and tape-out review process.

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Day 12: DFM

Day 14: Sign-off & Tape-out

EDA Tools — Innovus & ICC2