What is chip tape-out?

Tape-out is the final step of IC design — delivering the complete GDSII layout file to the foundry for manufacturing. The name comes from the era when final design data was written to magnetic tape. Modern tape-out packages include GDSII, netlist, timing constraints, test vectors, and a sign-off report proving all DRC, LVS, and timing checks are clean.

How long does chip tape-out take after final sign-off?

The physical tape-out process (reviewing and submitting data to foundry) takes 1–3 weeks. After submission, foundry manufacturing typically takes 8–16 weeks for the first silicon wafers to arrive. Total from tape-out to first silicon: 10–20 weeks depending on process node and foundry capacity.

What checks must pass before tape-out?

Before tape-out: DRC clean (zero violations), LVS clean (layout matches netlist), ERC clean (no floating nodes), formal equivalence (layout netlist matches RTL), STA passed at all MCMM corners with post-PEX parasitics, power analysis complete, DFM fill inserted, and antenna violations resolved.

Physical Design Day 14 — Sign-off & Tape-out

1. What is Tape-out?

Tape-out is the moment when the complete chip layout data is delivered to the foundry for manufacturing. The name originated from the era when final design data was literally written to magnetic tape. Today it's a digital delivery of a GDSII file — but the stakes are exactly the same.

The Highest-Stakes Deadline in Engineering

A tape-out is irreversible. Once the foundry begins exposing masks ($1M+) and running wafers ($500K/lot), errors are enormously expensive to fix. A missed DRC violation or timing bug that made it to silicon requires a full respin — costing millions and adding 6 months. Every item on the sign-off checklist exists because someone, somewhere, once shipped a chip with that bug.

2. Sign-off Verification Pipeline

Complete Sign-off Verification Flow

Physical Verification

DRC — Zero foundry design rule violations

LVS — Layout matches final netlist

ERC — No floating nodes, no bus fights

Antenna — All violations resolved

DFM — Fill inserted, redundant vias added

Electrical Sign-off

STA — All MCMM corners, post-PEX timing

Power — IR drop, EM, power budget met

Signal Integrity — Crosstalk, noise margin

Formal — Layout netlist ≡ RTL (equivalence)

CDC — All clock domain crossings verified

3. The Tape-out Package

The tape-out deliverable is not just a GDSII file. The foundry requires a complete package to begin manufacturing:

Deliverable	Format	Purpose
Layout database	GDSII / OASIS	Physical geometry for all mask layers
Netlist (sign-off)	Verilog / SPICE	Electrical connectivity reference for LVS
Sign-off STA report	PDF / HTML	Proves all timing constraints met
DRC clean report	Calibre report	Zero violations, foundry-certified tool
LVS clean report	Calibre nmLVS	Layout matches netlist
Layer map file	ASCII map	Maps design layers to foundry GDS layers
Fill GDS merge	GDSII	Combines design + standard cell GDS + fill
Test structure GDS	GDSII	Process monitor structures in scribe lane
PDK version record	Text file	Exact PDK version used for sign-off
Design rule waiver list	Text + justification	Any DRC waived violations with written justification

4. PDK Version Locking

The PDK (Process Design Kit) version must be locked before sign-off begins and must not change. Foundries periodically update PDKs with corrected models, new DRC rules, or revised standard cells. Using a different PDK version than what was used during implementation can:

Introduce new DRC violations from tightened rules
Change timing (updated cell models) and invalidate sign-off
Break LVS (cell layout changes)
Require full re-implementation — catastrophic schedule impact

PDK Version Tracking (production practice): Design start: Lock to PDK v1.5.2 Document in design_spec.txt: FOUNDRY: TSMC PROCESS: N5 PDK_VERSION: v1.5.2 PDK_LOCK_DATE: 2026-03-15 SIGN_OFF_TOOLS: DRC: Calibre 2023.1.7 + TSMC_N5_DRC_v1.5.2.svrf LVS: Calibre nmLVS 2023.1.7 + TSMC_N5_LVS_v1.5.2.svrf STA: PrimeTime 2023.12 + TSMC N5 TLU+ files v1.5.2 PEX: StarRC 2023.12 + tech_file v1.5.2 Never upgrade PDK after sign-off freeze without: 1. Full re-run of DRC + LVS on complete chip 2. Spot-check of timing on 3 representative corners 3. Written sign-off from PD lead + DV lead + Program manager

5. Tape-out Review Meeting

The tape-out review (TOR) meeting is the final gate before data delivery. All disciplines sign off in the same meeting — one person objecting can stop a tape-out.

TOR Meeting Agenda (Typical 4-hour meeting)

0:00–0:30

Physical Verification Summary — DRC/LVS sign-off status, waiver list reviewed

0:30–1:00

Timing Sign-off — Worst slack per corner, clock summary, critical path review

1:00–1:30

Power/IR/EM — Static/dynamic IR drop, EM violations, power budget

1:30–2:00

DV Status — Simulation coverage, formal verification, CDC status

2:00–2:30

Known Issues / Waivers — Every open item reviewed with risk assessment

2:30–3:30

Q&A / Escalations — Any team member can raise blocking concerns

3:30–4:00

Go/No-Go Decision — All stakeholders sign tape-out approval form

6. Common Tape-out Pitfalls

Pitfall	Root Cause	Prevention
DRC violation in PDK cell	Wrong cell GDS version merged	Lock PDK version; verify cell GDS matches tech.lef
LVS shorts after fill	Metal fill incorrectly touching signal net	Fill exclusion zones; LVS re-run after fill insertion
Timing fails post-PEX	RC parasitics higher than estimated	Always sign-off with PEX-extracted parasitics, not estimates
Missing test structures	Process monitor cells not added to scribe lane	Foundry checklist includes test structure requirement
Wrong PDK corner used	Fast corner used for setup; should be slow	Document MCMM corner set; tooling enforces correct corners
GDSII layer map error	Design layer 25 mapped to wrong foundry layer	Double-check layer map against foundry spec; run test layout

7. After Tape-out — The Manufacturing Timeline

From Tape-out to First Silicon (TSMC N5, typical)

Week 0

Tape-out data delivered to TSMC

Week 1–2

Foundry data prep, mask tape-out (OPC, mask write)

Week 3–4

Mask fabrication (e-beam write, inspect, qualify)

Week 5–14

Wafer processing (~80 mask steps: oxide, implant, metal, polish)

Week 15–16

Wafer electrical test (probe, speed sort, yield measurement)

Week 17–20

Die packaging, final test, first silicon delivery to design team

Final Tape-out Checklist (Master List)

✅ DRC: zero violations with foundry-certified Calibre ruleset
✅ LVS: clean — post-fill, post-ECO, final netlist match
✅ ERC: clean — no floating nets, no antenna unresolved
✅ Formal equivalence: layout netlist ≡ final RTL (Conformal/Formality)
✅ STA: all corners green with post-PEX, MCMM sign-off report
✅ Power/EM: signed off — static + dynamic IR within budget
✅ Signal integrity: crosstalk timing and noise checked
✅ CDC verified: all clock crossings formally verified
✅ DFM complete: fill inserted, redundant vias, OPC by foundry
✅ PDK version locked: documented and signed
✅ GDSII merged: design + cells + test structures + fill
✅ Layer map verified: test layout confirmed correct layer numbers
✅ Waiver list approved: every open item has written sign-off
✅ TOR meeting completed: all stakeholders signed go-ahead
✅ Data package delivered: GDSII + netlist + reports sent to foundry

Next — Day 15: Post-silicon validation — first silicon bring-up, ATE testing, scan chains, speed binning, yield analysis, and silicon debug strategies.

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Day 15: Post-Silicon Validation