What is power planning in physical design?

Power planning is the stage of physical design where engineers design the power delivery network (PDN) — the hierarchical system of metal rings, straps, and rails that distributes VDD and VSS from the chip pads to every standard cell. A well-designed PDN keeps IR drop (resistive voltage loss) below 5–10% of VDD at every cell, ensuring correct timing and reliable operation.

What is the difference between a power ring and a power strap?

A power ring runs around the periphery of a block or the full chip core, connecting to the power pads. It is wide and uses top metal layers (M8–M10) to handle the total chip current. Power straps are horizontal and vertical grid lines that branch off the ring and distribute current across the core area. Straps are narrower than the ring but still wide (2–10 µm) to limit resistance. Rails are the finest level — cell-pitch horizontal wires on M1/M2 that connect directly to standard cell VDD/VSS pins.

How do you calculate IR drop in a power grid?

IR drop = I × R, where I is the switching current of the cells drawing from that segment of the grid, and R is the resistance of the metal segment to the nearest via/pad. Resistance = ρ × L / (W × T), where ρ is resistivity, L is length, W is width, T is thickness. In practice, power grid analysis tools (Cadence Voltus, Ansys RedHawk) simulate the entire PDN as a resistor network with current sources attached at each cell, computing the voltage at every node.

What is electromigration and why does it limit strap width?

Electromigration (EM) is the gradual displacement of metal atoms caused by electron momentum transfer (the 'electron wind'). When current density exceeds the EM limit (typically 1–5 mA/µm for copper at 125 °C), voids form and the wire can open-circuit over time. Black's equation gives MTTF (mean time to failure). To fix EM, widen the strap (halving current density raises MTTF by 2×) or add vias so current splits across layers.

Power Planning & Power Grid Design in Physical Design — Day 16

1. Why Power Planning Is a First-Class Physical Design Step

Every chip failure mode ultimately comes back to power. If the power delivery network (PDN) drops too much voltage — a phenomenon called IR drop — logic gates switch slower than the timing model expects, setup violations appear at signoff, and the chip either fails at the rated frequency or fails completely. If metal wires carry too much current density — electromigration — they slowly degrade over years of operation until the chip dies in the field.

Power planning is therefore not an afterthought: it is done during floorplanning, before any standard cell is placed, because the PDN structure determines how much routing area is consumed, where macro blockages must go, and what the fundamental IR drop floor of the design will be.

<5%

Target static IR drop (% of VDD)

<10%

Target dynamic IR drop (% of VDD)

1–5 mA/µm

Cu EM current density limit (125 °C)

M7–M10

Typical power ring/strap metal layers

The PDN Hierarchy

Modern SoC power grids are a four-level hierarchy, each level progressively finer and closer to the cells:

Level	Structure	Metal Layers	Width (28nm node)	Purpose
L1 — Bump/Pad	C4 flip-chip bumps or wire-bond pads	RDL / top metal	50–100 µm pitch	Connect package to die
L2 — Power Ring	Wide ring around chip core or block	M8–M10 (top metals)	10–40 µm	Distribute power from pads to straps
L3 — Power Straps	H/V grid across core	M5–M9	2–10 µm	Reduce sheet resistance across die
L4 — Power Rails	Cell-pitch H wires (VDD/VSS rows)	M1–M2	0.1–0.5 µm	Connect directly to cell VDD/VSS pins

Fig 1: Power Delivery Network hierarchy — rings (M9/M10) feed vertical and horizontal straps (M6–M8), which feed the cell-pitch rails (M1/M2).

2. Power Ring and Strap Design

2.1 Power Ring Sizing

The power ring must carry the entire chip current from the pads to the straps. Sizing starts from the power budget:

I_chip = P_total / VDD (e.g. 5W / 0.8V = 6.25 A) R_ring = ΔV_budget / I_chip (e.g. 20mV / 6.25A = 3.2 mΩ) R_metal = ρ × L / (W × T) → W = ρ × L / (R_ring × T) ρ_Cu = 1.7 × 10⁻⁸ Ω·m (bulk; on-chip ~2.2 × 10⁻⁸ due to grain boundaries) T = foundry-defined metal thickness (e.g. 0.9 µm for M9 at 28nm) L = ring perimeter segment length

In practice, power ring widths range from 10 µm for small blocks to 40–80 µm for full-chip rings carrying 10+ amperes. The ring runs on at least two metals (e.g. M9 for VDD, M8 for VSS) so they can be parallel without shorting.

2.2 Power Strap Pitch and Width

Straps create the grid interior. The key tradeoff: narrower pitch → lower IR drop but more routing blockage. A common starting point is to target IR drop contribution from straps of ≤ 3 mV, then calculate the required strap count from the current density per strap.

Parameter	Typical Range (28nm)	5nm FinFET Range	Effect of Increasing
Strap pitch	20–60 µm	5–15 µm	More straps → lower IR, less routing area
Strap width	2–8 µm	0.3–1 µm	Wider → lower resistance, lower EM risk
Metal layer	M5–M8	M4–M6	Higher metal → lower ρ (thicker), less congestion
VDD:VSS ratio	1:1 alternating	1:1 alternating	Equal pitch minimizes loop inductance

2.3 Strap Pattern Strategies

Uniform grid: Fixed pitch H and V straps across the full core. Simple to implement; works well for uniform activity designs.
Activity-aware grid: Dense straps over high-switching blocks (multiplier arrays, SRAM), sparse elsewhere. Reduces total routing blockage while fixing hotspots.
Macro-aware straps: Straps must route over macros (memories, IPs) that have fixed internal power connections. The top-level straps connect at the macro's power pins defined in its LEF/abstract view.
Via stacks: Every strap intersection with the ring and with rails requires a via stack (M1–M2–…–M9). Via resistance is significant; use maximum legal via arrays to minimize it.

Tcl — Cadence Innovus power ring + strap commands

# 1. Add VDD/VSS power ring around core
addRing \
  -nets {VDD VSS} \
  -layer_top    M9 \
  -layer_bottom M9 \
  -layer_left   M8 \
  -layer_right  M8 \
  -width        20 \
  -spacing      5  \
  -offset       2

# 2. Add power straps across the core (horizontal M6, vertical M7)
addStripe \
  -nets          {VDD VSS} \
  -layer         M7 \
  -direction     vertical \
  -width         4 \
  -spacing       2 \
  -set_to_set_distance 40 \
  -start_offset  20

addStripe \
  -nets          {VDD VSS} \
  -layer         M6 \
  -direction     horizontal \
  -width         3 \
  -spacing       2 \
  -set_to_set_distance 30 \
  -start_offset  15

# 3. Connect standard cell rails to straps (globalNetConnect)
globalNetConnect VDD -type pgpin -pin VDD -all
globalNetConnect VSS -type pgpin -pin VSS -all

3. IR Drop Analysis — Static vs Dynamic

IR drop is the resistive voltage loss from the power source to the cells. There are two flavors with very different analysis methods:

Type	Cause	Analysis Method	Typical Budget	Fix Strategy
Static IR drop	DC leakage current through grid resistance	DC analysis: V = I_leakage × R_grid	< 5% VDD	Widen straps, add ring layers
Dynamic IR drop	Simultaneous switching (SSO) creates large current transients	Transient simulation: L×dI/dt + I×R	< 10% VDD	Add decoupling capacitors, stagger clocks
Self-heating (EM risk)	High current density → Joule heating → accelerates EM	Thermal + EM co-analysis	J < J_limit (125°C)	Widen wires, add vias, parallel paths

IR Drop Hotspot — What the Map Looks Like

Fig 2: IR drop heatmap. Green = safe, yellow = warn, red = violation. Hotspots (58–62 mV) exceed the 40 mV budget and need more straps or decap placed nearby.

The Timing Impact of IR Drop

A 50 mV drop on a 0.8 V rail is 6.25%. Cell delay increases roughly linearly with reduced VDD — on a 0.8 V nominal, 50 mV drop adds ~8–10% delay to cells in that region. If your hold budget is tight, this can cause functional failures at speed even if the STA passed at nominal VDD.

How to Fix IR Drop Violations

Add more straps in the violating region — halving strap pitch roughly quarters the IR drop in that area.
Widen existing straps — width doubling halves resistance and IR drop proportionally.
Add higher-metal straps — M9 has 3–5× less sheet resistance than M5; using higher metals delivers current more efficiently.
Insert decoupling capacitors — fixes dynamic IR; described in Section 5.
Stagger clock domains — if the hotspot is driven by simultaneous clock edges switching millions of flops, stagger launch edges across domains to spread the current transient in time.
Reduce functional switching — add clock gating to suppress switching in idle blocks (also reduces dynamic power).

4. Electromigration — Black's Equation and Wire Sizing

Electromigration (EM) is the directed motion of metal atoms caused by momentum transfer from conduction electrons (the "electron wind"). In copper interconnects, this creates two failure modes over time: voids (where metal was) that increase resistance and eventually open-circuit, and hillocks (where metal piled up) that can create shorts to adjacent lines.

Black's Equation — Mean Time to Failure (MTTF): MTTF = A × J⁻ⁿ × exp(Ea / kT) Where: A = process-specific pre-exponential constant J = current density (mA/µm²) n = current density exponent ≈ 2 (for void-dominated EM) Ea = activation energy ≈ 0.9 eV (Cu) / 0.7 eV (Al) k = Boltzmann constant = 8.617 × 10⁻⁵ eV/K T = temperature in Kelvin Key insight: doubling J reduces MTTF by 4× (n=2) raising T by 10°C reduces MTTF by ~2×

EM Design Rules in Practice

Wire Type	J_limit (mA/µm) at 125°C	Fix if violated
Power strap (unidirectional DC)	1.0–2.0	Widen strap, add parallel via path
Power rail M1/M2	0.5–1.0	Add more vias, increase rail width
Signal wire (bidirectional AC)	4–8 (RMS, AC relaxed rule)	Wider wire, reduce drive strength
Via stack (via current)	0.1–0.5 mA/via	Add via array (more vias in parallel)

Why Vias Are Often the EM Bottleneck

A single via may carry only 0.1–0.5 mA before exceeding its EM limit. A 4 µm strap on M7 might be EM-clean (it's wide), but the single via connecting it to M6 below carries all the current through a tiny contact area. Always check via EM, not just wire EM. Fix: use via arrays (e.g. 4×4 = 16 vias in parallel) to spread the current load.

Tcl — Innovus EM/IR analysis trigger (pre-sign-off check)

# Set power analysis mode
setAnalysisMode -analysisType onChipVariation -cppr both

# Load activity file (switching probability per net)
read_activity_file -format VCD design_activity.vcd

# Run static IR and EM check (quick pre-Voltus check)
analyzeIRDrop \
  -nets          {VDD VSS} \
  -temperature   125 \
  -report_violations_only yes \
  -out_file      ir_drop_report.rpt

# View violations in GUI
report_ir_drop -min_violation 10 -max_violation 200

5. Decoupling Capacitors — Taming Dynamic IR Drop

Decoupling capacitors (decaps) act as local charge reservoirs. When a large block switches simultaneously, instead of drawing a huge current spike from the distant power ring (which takes nanoseconds to respond due to inductance), the cells draw from decap cells placed nearby that discharge instantly.

Types of Decap Cells

Type	Construction	Capacitance/area	Use Case
Standard decap cell	NMOS transistor, gate = VDD, source/drain = VSS → gate-oxide cap	High (gate oxide thin)	Placed in filler cell slots between standard cells
Well-tap decap	Combined well-tap + decap in one cell	Medium	Rows requiring both well tie and decap
MOM cap (Metal-Oxide-Metal)	Interdigitated metal comb structure	Lower density, no oxide risk	Blocks where gate-oxide reliability is marginal
MIM cap	Dedicated metal-insulator-metal layer	Medium	Analog domains, I/O ring

Decap Placement Strategy

Target decap density: 10–20% of core area in high-activity blocks, 3–5% in low-activity regions.
Placement proximity: Decap must be within ~50–100 µm of the cells it serves — LC resonance limits how far charge can travel within a clock period.
Gate-oxide reliability: At 5nm/3nm nodes, gate-oxide breakdown voltage is close to VDD. Use only PDK-approved decap cells; custom NMOS decaps can cause oxide stress.
Leakage trade-off: NMOS decaps have large gate leakage at advanced nodes. Over-inserting decap can increase static power by 5–15%. Use the tool's optimized decap insertion commands.

Tcl — Cadence Innovus decap insertion

# Add decap cells in empty filler slots — run after placement
addDecap \
  -cell_list     {DCAP4 DCAP8 DCAP16 DCAP32} \
  -total_cap     2.0e-9 \
  -target_cap    2.5e-9 \
  -distribute_location user_defined \
  -region        {100 100 800 700}

# Alternatively: activity-driven decap (requires VCD/power intent)
addDecap \
  -cell_list     {DCAP8 DCAP16} \
  -voltage_domain VDD \
  -target_dynamic_ir_drop 0.05   ;# 5% VDD target

# Check result
report_power -rail_analysis

6. Power Domains, Voltage Islands & UPF

Modern SoCs are not a single-voltage chip. A smartphone SoC may have 8–12 distinct power domains running at different voltages or completely powered off when idle. UPF (Unified Power Format, IEEE 1801) is the standard that describes this multi-voltage intent in a file that synthesis, PnR, and sign-off tools all consume.

Key UPF Concepts

UPF Construct	What It Does	Physical Meaning
`create_power_domain`	Defines a logic region with its own supply	Area enclosed by power ring or strap set
`create_supply_net`	Declares a named supply rail	VDD1, VDD_CPU, VDD_GPU, VDDIO…
`create_power_switch`	Power gating transistor (header/footer)	MTCMOS header cell in row between on/off domain
`create_isolation_cell`	Clamps signals crossing powered→off domain	ISO cells at domain boundary; clamp to 0 or 1
`create_level_shifter`	Converts voltage between domains	LS cells at boundary between VDD1 and VDD2 domains
`create_retention_register`	Saves state when domain powers down	Retention FF (bubble/balloon FF) with shadow latch on always-on supply

Fig 3: Multi-voltage SoC power domains. Each domain has its own supply rail, isolation cells at boundaries, and optional power switch (MTCMOS header).

UPF — power domain and isolation definition

# Always-on top domain
create_power_domain PD_TOP -include_scope

# GPU domain — can be power-gated
create_power_domain PD_GPU \
  -elements {u_gpu} \
  -scope top

# Supply rails
create_supply_net VDD_AON -domain PD_TOP
create_supply_net VDD_GPU -domain PD_GPU

# Power switch (MTCMOS header)
create_power_switch SW_GPU \
  -domain      PD_GPU \
  -input_supply_port  {vin VDD_AON} \
  -output_supply_port {vout VDD_GPU} \
  -control_port       {sleep gpu_sleep_n} \
  -on_state           {on_state  vin {!sleep}} \
  -off_state          {off_state {} {sleep}}

# Isolation strategy at PD_GPU output
create_isolation_cell ISO_GPU \
  -domain      PD_GPU \
  -applies_to  outputs \
  -clamp_value 0 \
  -isolation_supply_net VDD_AON \
  -isolation_signal     gpu_iso_en \
  -isolation_sense      high

7. PDN Sign-Off — Voltus and RedHawk Flow

Pre-signoff checks in Innovus catch obvious problems, but full PDN sign-off requires dedicated power integrity tools — Cadence Voltus or Ansys RedHawk. These tools solve a resistor-network equation with millions of nodes and use VCD-derived switching activity to model dynamic currents accurately.

Voltus Flow (Cadence)

Step	Input	What Voltus Does	Output
1. DEF/SPEF import	Post-route DEF, RC SPEF	Build resistor network from metal/via geometry	Internal PDN netlist
2. Power intent	UPF + Liberty (.lib)	Map cells to supply rails, leakage per cell	Cell current map
3. Activity annotation	VCD or switching probability	Assign dynamic current sources per cell	Annotated netlist
4. Static IR analysis	DC leakage	Solve V=IR across PDN — find worst node	IR map, violation report
5. Dynamic IR analysis	VCD transients	Transient simulation — finds voltage droop magnitude	Time-domain droop waveforms
6. EM check	Current density per wire	Compare J to PDK EM limit; compute MTTF	EM violation report
7. ECO feedback	Violation list	Suggest strap additions, decap placement	ECO script for Innovus

Tcl — Voltus static IR + EM signoff invocation

# Run from Cadence Voltus environment
set_db design_process_node 28
read_physical -def chip_postroute.def
read_parasitics -format spef chip.spef.gz

# Load power intent
read_power_intent -cpf design.cpf  ;# or -upf design.upf

# Set activity for dynamic analysis
read_activity_file -format VCD sim_output.vcd \
  -scope top -start 1000ns -end 2000ns

# Static IR analysis
analyze_power_rail \
  -rail_name {VDD VSS} \
  -temperature 125 \
  -type static \
  -report chip_static_ir.rpt

# Dynamic droop analysis
analyze_power_rail \
  -rail_name {VDD} \
  -type dynamic \
  -time_range {1000ns 2000ns} \
  -report chip_dynamic_ir.rpt

# EM sign-off
check_em \
  -temperature  125 \
  -nets         {VDD VSS} \
  -report       em_violations.rpt \
  -max_violations 0

Real Chip Numbers — Apple A17 and AMD EPYC

Metric	Apple A17 Pro (3nm)	AMD EPYC Genoa (5nm)	Intel Xeon SPR (Intel 7)
TDP	~8W (mobile)	~360W (server)	~350W
Supply voltage	~0.7–1.0V (DVS)	~0.7–1.05V	~0.75–1.0V
Peak current	~10–12A	~360A	~380A
IR drop budget	<30 mV static	<40 mV static	<50 mV static
Power domains	12+ (CPU/GPU/NE/ISP…)	Chiplet-level + core-level	Tile-based + ring-level
Bump/pad pitch	130 µm (C4 flip-chip)	130 µm	100 µm (FOVEROS)

Server Chips Have an Entirely Different PDN Problem

AMD EPYC draws 360W at ~0.85V — that's 420 amperes total. At this scale, package and PCB resistance (not just on-chip) become the dominant IR drop sources. The VRM (Voltage Regulator Module) must be positioned within centimetres of the socket, and the package substrate power planes are as thick as 50–100 µm copper. On-chip PDN design is just one layer of a multi-board stack problem.

8. Common Power Planning Mistakes and How to Avoid Them

Mistake	Consequence	Prevention
Under-sized power ring	IR drop concentrated at ring segments; all cells downstream suffer	Size ring for worst-case I × R in first iteration; check with Innovus before placement
Missing via arrays at strap–ring intersection	EM failure at via after 2–3 years in field	Always use max-via array at power connections; check EM at via in Voltus
Straps blocked by macro placement	Current forced to route around macros → long path → high R	Plan strap grid BEFORE placing macros; reserve strap channels in floorplan
No isolation cells at power domain boundary	Unknown logic levels from powered-off domain corrupt active domain	Check UPF isolation coverage in DC/Genus; verify in Voltus power intent check
Excessive decap leakage	Static power increases 10–15% above power budget	Use tool-controlled decap insertion with leakage limit constraint
Ignoring dynamic IR at clock edges	Setup violations appear only at high frequencies	Always run dynamic IR with representative VCD; check droop at clock edge

9. Interview Q&A — Power Planning

#	Interview Question	Strong Answer Points
1	What is the difference between static and dynamic IR drop?	Static = DC leakage × R_grid (permanent). Dynamic = transient SSO current spike + inductance effect (L·dI/dt). Dynamic is usually 2–3× worse. Dynamic requires VCD for analysis.
2	How do you size a power strap?	Start from power budget → peak current → target IR (5% VDD) → R_max = ΔV/I → W = ρL/(R_max × T). Then verify EM: J = I/W < J_limit.
3	What is Black's equation and what does it govern?	MTTF = A·J⁻ⁿ·exp(Ea/kT). Governs electromigration MTTF. Key: doubling J reduces MTTF by 4×; raising temp 10°C ~halves MTTF. Used to set current density limits on power wires and vias.
4	What is an isolation cell and when is it needed?	ISO cell clamps a signal from a powered-off domain to a known value (0 or 1) so the always-on domain doesn't see floating/corrupted inputs. Required at every output crossing from a power-gated domain.
5	What is the purpose of a decoupling capacitor in a power grid?	Decap stores local charge that can supply switching current instantly, preventing voltage droop. It bridges the time between when a current transient occurs and when the distant power rail can respond through its RC network.
6	What tools do you use for PDN sign-off?	Cadence Voltus (static/dynamic IR, EM, thermal), Ansys RedHawk-SC. Pre-signoff quick check inside Innovus (analyzeIRDrop). Both tools require DEF, SPEF, UPF, and VCD activity.

10. Day 16 Power Planning Checklist

Power Grid Design Sign-Off Checklist

☐ Power ring sized for peak chip current with <5% VDD drop across ring
☐ Strap pitch set to meet IR drop budget in worst-case activity region
☐ Via arrays (not single vias) at all strap–ring and strap–rail intersections
☐ Static IR analysis run in Innovus — no violations >5% VDD
☐ Dynamic IR analysis run in Voltus with representative VCD — droop <10% VDD
☐ EM check passed for all power straps, rails, and vias at 125 °C
☐ Decap inserted in IR hotspot regions — dynamic droop reduced to budget
☐ Decap leakage within power budget allowance
☐ UPF loaded and validated — all power domains have correct supply connections
☐ Isolation cells present at all power-gated domain output boundaries
☐ Level shifters inserted at all voltage-crossing signal paths
☐ Retention registers used for state-critical flops in power-gated domains
☐ Voltus sign-off: zero static IR violations, zero EM violations

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