The final gate before GDSII hits the foundry. Comprehensive signoff: static and dynamic IR drop, electromigration limits, DRC/LVS physical verification, STA across all PVT corners, antenna repair, metal fill — and the complete 30-point tapeout checklist used by production ASIC teams.
Signoff is not a single tool or a single run — it is a sequence of independent verification checks, each of which must pass before the GDSII is released to the foundry. Miss any one of them and you risk silicon failure, yield loss, or reliability problems that don't show up until chips are in the field.
IR drop is the voltage difference between the power pad (where the ideal VDD/VSS is applied) and the standard cell power pins deep in the chip core. Even a small resistance in the power grid (rings, straps, rails) multiplied by the large currents in a modern chip produces millivolts of drop — enough to slow down timing paths and cause failures in the actual silicon.
# Step 1: Static IR drop — import routed design
set_db init_power_nets {VDD}
set_db init_ground_nets {VSS}
read_db post_route.db
read_spef post_route.spef
# Set switching activity from VCD or ADB
read_activity_file -format vcd -scope top simulation_vectors.vcd
# Run static IR analysis
analyze_power_rail -rail_name VDD -type avg \
-report_file reports/static_ir.rpt
report_power_rail_analysis -file reports/static_ir_summary.rpt
# Step 2: Dynamic IR — needs vector-based switching activity
set_db analysis_type onchip_variation
analyze_rail -rail_name VDD -type dynamic \
-waveform_interval 0.01 \
-worst_time_window 1.0 \
-report_file reports/dynamic_ir.rpt
# Check violations
check_rail -min_voltage [expr {0.95 * $VDD_nominal}] -rail VDD
report_rail_violations -type voltage_drop > reports/ir_violations.rptDynamic IR drop causes setup violations that only appear at the exact clock edge when maximum simultaneous switching occurs. Static timing analysis uses nominal VDD; if the real VDD at that moment is VDD - 100mV, setup margin evaporates. This is why chips that pass pre-silicon timing analysis can fail in silicon — the PDN was inadequate for the worst-case switching pattern. Fix: add decoupling capacitors near high-activity blocks and use vectorbased dynamic IR analysis with realistic toggle patterns.
Electromigration is the primary long-term reliability failure mechanism in metal interconnects. Electron flow in a metal wire exerts a drag force on metal atoms (momentum transfer). Over years of operation, atoms pile up at one end of the wire (hillock) and deplete at the other (void). When a void grows large enough, it opens the circuit — the chip dies.
| Metal Layer | Typical Width | J_max (10yr, 105°C) | EM Violation Fix |
|---|---|---|---|
| M1 (local interconnect) | 50–100 nm | 1–2 mA/µm | Widen wire or parallel wires |
| M2–M3 (routing) | 80–150 nm | 2–4 mA/µm | Add parallel wire on same/adj layer |
| M4–M6 (intermediate) | 120–300 nm | 4–8 mA/µm | Widen, or move to higher layer |
| M7–M9 (power) | 0.5–5 µm | 8–15 mA/µm | Add power strap or widen ring |
| Via (single) | per via | 0.3–0.5 mA | Add parallel vias (via array) |
| Contact | per contact | 0.1–0.3 mA | Multiple contacts per pin |
# EM signoff — check all wires and vias against foundry J_max limits
# In Innovus post-route
setAnalysisMode -analysisType onChipVariation
setDesignMode -process 28 -node 28
# Read EM limits from library (PDK-provided)
loadEmRules -file pdk/28nm/em_rules.lib
# Run static EM check (RMS current for AC signals, average for DC power)
analyzeEM -type avg -reportFile reports/em_avg.rpt ;# power nets
analyzeEM -type rms -reportFile reports/em_rms.rpt ;# signal nets (AC)
analyzeEM -type peak -reportFile reports/em_peak.rpt ;# signal nets (peak)
# Report violations
report_em_violations -limit 100 > reports/em_violations.rpt
# Fix: for signal net EM violations, Innovus can ECO-widen
foreach_in_collection net [get_em_violated_nets] {
set_db $net .min_width [expr {[get_db $net .min_width] * 1.5}]
}
ecoRoute -modifyOnlyDRCViolations
# Verify via EM — add via arrays where single via violates
check_drc -type em_via
routeECO -fixEMViaDRC (Design Rule Check) verifies that every polygon in the GDSII satisfies the foundry's geometric manufacturing rules — minimum wire width, minimum spacing, minimum enclosure of vias, metal density requirements, and hundreds of other constraints. LVS (Layout vs. Schematic) verifies that the circuit implemented in the layout (extracted from GDSII) matches the intended netlist — every transistor, every connection.
| Rule Category | Example Rule | Why It Exists |
|---|---|---|
| Minimum width | M1.W ≥ 80nm | Lithography resolution limit — narrower wires are unreliable |
| Minimum spacing | M1.S ≥ 80nm | Prevent shorts between adjacent wires |
| Via enclosure | V1 enclosure by M1 ≥ 20nm | Alignment tolerance — via must be fully inside lower metal |
| Metal density | 60% ≤ M1 density ≤ 85% | CMP (Chemical Mechanical Planarization) requires uniform surface |
| Notch rule | M1 notch ≥ 80nm | Concave corners cause lithographic rounding that can close the notch |
| Well tap distance | N-well tap ≤ 2µm from any PMOS | Latch-up prevention — substrate potential must be clamped |
| End-of-line | EOL spacing ≥ 120nm | Line-end rounding creates local field enhancement — causes shorts |
# Run Calibre DRC (from shell, or source inside Innovus)
calibre -drc \
-hier \
-turbo 16 \
pdk/28nm/calibre_drc.runset << 'EOF'
LAYOUT PATH "chip_top_final.gds"
LAYOUT SYSTEM GDSII
LAYOUT PRIMARY "chip_top"
DRC RESULTS DATABASE "drc_results.db"
DRC SUMMARY REPORT "reports/drc_summary.rpt"
DRC MAXIMUM RESULTS 500
DRC MAXIMUM VERTEX 128
EOF
# Run Calibre LVS
calibre -lvs \
-hier \
-turbo 16 \
pdk/28nm/calibre_lvs.runset << 'EOF'
LAYOUT PATH "chip_top_final.gds"
SOURCE PATH "chip_top_netlist.spi"
SOURCE SYSTEM SPICE
LVS REPORT "reports/lvs_report.rpt"
LVS REPORT OPTION FULL
LVS REDUCTION YES
LVS RECOGNIZE GATES ALL
EOF
# Check results: LVS must show "CORRECT" at bottom of report
grep -A 2 "LVS Comparison" reports/lvs_report.rptPre-route timing uses estimated (ideal) wire loads. Signoff STA uses the actual post-route SPEF parasitics — real wire resistance and capacitance extracted from the final layout. The difference can be 20–40% in path delay — paths that were clean at 100ps of slack pre-route can have 0ps or negative slack after extraction.
# PrimeTime signoff — SS 0.9V 125°C (worst setup corner)
set_app_options -name time.enable_aocv -value true
# Read design
read_verilog chip_top.v
read_db [list cells_ss_0p9v_125c.db io_cells.db]
link_design chip_top
# Apply constraints
read_sdc chip_top.sdc
set_operating_conditions SS_0P9V_125C
# Apply post-route parasitics (SPEF)
read_parasitics -format SPEF \
-keep_capacitive_coupling \
chip_top_max.spef
# AOCV derates
set_timing_derate -early 0.95 -cell_delay -data_path
set_timing_derate -late 1.05 -cell_delay -data_path
set_timing_derate -early 0.95 -cell_delay -clock_path
set_timing_derate -late 1.05 -cell_delay -clock_path
# Update timing
update_timing -full
# Report
report_timing -path_type full_clock -delay_type max \
-nets -input_pins -significant_digits 4 \
-max_paths 50 > reports/setup_timing_signoff.rpt
report_constraint -all_violators > reports/constraint_violations.rpt
report_qor > reports/qor_summary.rpt
# Hold corner (FF 1.1V -40°C)
set_operating_conditions FF_1P1V_M40C
read_parasitics chip_top_min.spef
update_timing
report_timing -delay_type min -max_paths 50 > reports/hold_timing_signoff.rptDuring fabrication, metal layers are deposited and etched one at a time from the bottom up. Long metal wires connected to a transistor gate can accumulate charge from the plasma etch process before the upper metal layers (and their connections to diffusion — the natural "antenna diode") are deposited. If enough charge builds up on the gate oxide, it can permanently damage the thin gate oxide. This is the antenna effect.
CMP (Chemical Mechanical Planarization) is the polishing step that flattens each metal layer during fabrication. CMP uniformity depends on local metal density — areas with too little metal polish faster (dishing), areas with too much polish slower (erosion). Both cause height variation that affects the next layer's lithography. Foundries specify a minimum and maximum metal density window (e.g. 20–80% per 50×50 µm window) for every metal layer.
# Add metal fill for CMP density control
# Run after routing is complete and antenna check is clean
# Configure fill parameters per foundry spec
setMetalFill -layer {M1 M2 M3 M4 M5 M6 M7 M8} \
-minDensity 20 \
-maxDensity 80 \
-windowSize 50 \
-windowStep 25 \
-fillCellName METALFILL_D2
# Run fill insertion
addMetalFill -layers {M1 M2 M3 M4 M5 M6 M7 M8}
# Verify density after fill
checkMetalFill -layer {M1 M2 M3 M4 M5 M6 M7 M8} \
-reportFile reports/metal_density.rpt
# Re-run DRC after fill to check fill didn't create new violations
verifyConnectivity -type special
report_drc -type fill > reports/post_fill_drc.rptEvery ASIC team has a tapeout checklist. This is a distillation of the standard checks used at leading foundry partners. Every item must be green before the GDSII is released.
| Day | Topic | Core Concept |
|---|---|---|
| 1–5 | Floorplanning through Placement | Die area, utilization, macro placement, timing-driven placement |
| 6–10 | CTS through Routing | Clock tree H-tree/skew, NDR rules, global→detailed routing, DRC |
| 11–15 | STA basics through Timing Closure | Setup/hold, OCV, ECO, WNS/TNS convergence |
| 16 | Power Planning | PDN hierarchy, ring/strap sizing, IR drop, decap, UPF |
| 17 | Clock Tree Synthesis | H-tree, skew budget, useful skew, hold fix, ICG, NDR |
| 18 | Signal Integrity | Coupling cap, Miller effect, crosstalk delay/glitch, SPEF, shielding |
| 19 | Low Power Design | Multi-Vt, clock gating ICG, MTCMOS, retention FF, UPF flow |
| 20 | Signoff & Tapeout | IR drop/EM signoff, DRC/LVS, STA all corners, tapeout checklist |
You've now covered the complete physical design flow from RTL netlist to GDSII tapeout across 20 days. The topics in Days 16–20 — power planning, CTS, signal integrity, low-power design, and signoff — are the areas where experienced PD engineers spend 80% of their time on real chips. Master these and you're ready for a physical design engineer role at any semiconductor company.
| # | Question | Answer Points |
|---|---|---|
| 1 | What is the difference between static and dynamic IR drop? | Static: average current × PDN resistance — shows steady-state voltage drop from average power consumption. Dynamic: instantaneous voltage droop from a spike in current when many cells switch simultaneously at a clock edge — 2–3× larger than static, lasts 100–500 ps, and causes the actual setup timing failures seen in silicon. Dynamic IR requires vectorbased analysis with real toggle patterns. |
| 2 | What does Black's equation tell you? | MTTF = A × J^(-n) × exp(Ea/kT). It predicts how long a metal wire will survive before electromigration causes a void/open. J is the key design variable — reduce current density (by widening the wire or adding parallel wires) to exponentially increase MTTF. Temperature has an enormous effect: 40°C increase can reduce lifetime by 10×. |
| 3 | What causes an antenna violation and how do you fix it? | During plasma etching, a long metal wire connected to a gate accumulates charge (like a radio antenna). If the charge is large enough (antenna ratio > foundry limit), it damages the gate oxide permanently. Fix by (1) jumping the wire to a higher metal layer that is connected to diffusion earlier, or (2) adding an antenna diode next to the gate to provide a discharge path during etch. |
| 4 | Why is LVS important if DRC already passes? | DRC only checks geometric rules — it does not verify the circuit is connected correctly. LVS compares the actual transistor connections extracted from the GDSII against the intended netlist. A DRC-clean layout can still have a missing via (open circuit), an unintended short between two nets, or cells from the wrong library version — all invisible to DRC but caught by LVS. |
| 5 | What PVT corner do you use for setup signoff and why? | SS/0.9V/125°C: slow-slow process corner (transistors are slowest), minimum supply voltage (drives are weakest), and maximum temperature (mobility degrades, Vt shifts). This represents the absolute worst-case delay for any timing path. Hold signoff uses FF/1.1V/-40°C: fast-fast process + maximum voltage + cold temperature gives the shortest clock-to-Q and combinational delays — worst case for hold. |
| 6 | What happens if you tapeout with DRC violations? | The foundry will typically refuse to fabricate the chip or fabricate with a disclaimer. Even "minor" violations can cause yield problems: a metal spacing violation that survives the mask process might be a real short on some dies (random process variation can close the gap). On advanced nodes (7nm and below), even a single systematic DRC violation can result in 0% yield. All violations must be resolved or explicitly waived by the foundry. |