Verification Engineering

SystemVerilog for
Functional Verification

From SVA assertions to constrained-random testbenches and UVM — everything a chip verification engineer needs, explained with real Verilog and SystemVerilog code.

5
Topics
SVA
Assertions
UVM
Methodology
Free
Always
SystemVerilog Verification Flow
DUT (RTL Design) DRIVER Drives stimulus MONITOR Captures output SCOREBOARD SVA ASSERTIONS interface interface COVERAGE
All Topics

SystemVerilog Series

Five focused guides — start with SVA if you know Verilog, or begin at Classes if you're moving into OOP-based verification.

SV-01
SystemVerilog Assertions (SVA)
Immediate vs concurrent assertions, sequence operators (##N, [*N], |->), property blocks, disable iff, $rose/$fell/$stable, and binding assertions to RTL modules. Includes 8 real-world examples.
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SV-02
Classes & Object-Oriented Programming
Classes, objects, constructors, inheritance, polymorphism, virtual methods, abstract classes, and handles in SystemVerilog. OOP concepts mapped to verification use cases like transaction classes and driver hierarchies.
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SV-03
Constrained-Random Verification
rand/randc, constraint blocks, constraint solving, soft constraints, inline constraints, pre_randomize/post_randomize, seed control, and directed vs constrained-random test strategies. Includes AXI transaction example.
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SV-04
Functional Coverage
Covergroups, coverpoints, bins, cross coverage, wildcard bins, ignore_bins, illegal_bins, sampling events, and $get_coverage. Understand the difference between code coverage and functional coverage and how to drive closure.
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SV-05
UVM Basics — Universal Verification Methodology
UVM component hierarchy (uvm_env, uvm_agent, uvm_driver, uvm_monitor, uvm_scoreboard), factory pattern, TLM ports, sequence-sequencer-driver flow, and phase control. Build your first UVM testbench from scratch.
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SystemVerilog vs Verilog — Key Additions

FeatureVerilogSystemVerilogUse In Verification
Data typeswire, reg, integerlogic, bit, byte, int, enum, structCleaner TB variables
Object-orientedNot supportedclass, extends, virtualReusable transaction objects
Randomization$random (no constraints)rand, randc, constraint blocksConstrained-random stimulus
AssertionsNot built-inassert, assume, cover, property, sequenceProtocol checking, coverage
CoverageNot built-incovergroup, coverpoint, crossFunctional coverage closure
Interfacesport lists onlyinterface, modport, clocking blockClean DUT-TB connection
Queues & arraysFixed arrays onlydynamic array, queue [$], assoc arrayScoreboards, expected models
Processesfork-join onlyfork-join_any, fork-join_none, disable forkParallel stimulus generation

Recommended Learning Path

1
Know Verilog first — Complete the 15-tutorial Verilog series if you haven't already. SV verification builds on Verilog RTL concepts.
2
Start with SVA — Assertions (SV-01) can be added to any Verilog testbench immediately. High payoff, low barrier.
3
Learn Classes + Randomization together — SV-02 and SV-03 form the OOP + stimulus pair that makes constrained-random verification work.
4
Add Functional Coverage — SV-04 turns your random tests into measured, closeable verification plans.
5
Finish with UVM — SV-05 ties everything together into the industry-standard methodology used at every major semiconductor company.
Related Series:
Verilog Tutorials (15) RTL Design Patterns AXI4 Protocol Interview Prep