APB Slave Register Interface

Verilog problems / Protocols & Interfaces

What you must build

A minimal AMBA APB slave: 4 registers, zero wait states — and the two-phase setup/access handshake that decides exactly when a write is allowed to land.

Engineers use “APB Slave Register Interface” as a building block in protocols & interfaces. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  psel,
  input  penable,
  input  pwrite,
  input  [1:0] paddr,
  input  [7:0] pwdata,
  output [7:0] prdata,
  output pready
);

Why this shows up in interviews

APB Slave Register Interface sits under Protocols &amp; Interfaces (sequential, protocol, amba). Concept: APB splits every transfer into a SETUP phase ( psel asserted, penable still low) and an ACCESS phase one cycle later ( penable now high too) — the actual register write must only commit during ACCESS: if(psel && penable && pwrite) regs[paddr]<=pwdata; . Dropping the penable check and writing on psel && pwrite alone commits the write a full cycle too early, during SETUP — a genuine APB protocol violation that happens to still "work" in simple single-transfer tests, which is exactly why it's a dangerous bug to leave in.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• CRC-8 Generator (poly 0x07) — Compute an 8-bit CRC over a byte using the classic 0x07 polynomial (CRC-8-CCITT) — the same bit-serial algorithm behind this catalog's CRC-4, scaled up to a full byte.
• SPI Mode Selector (CPOL/CPHA) — Decode SPI's 4 clocking modes from CPOL and CPHA into the two facts a controller actually needs: what the clock idles at, and which edge samples data.
• AXI4-Lite Write Channel FSM — Accept an address+data write beat, then hold the response channel until the master acknowledges — the handshake FSM behind every AXI4-Lite peripheral.
• AXI4-Lite Read Channel FSM — The read-side twin of this catalog's AXI4-Lite write FSM: accept an address, then hold the data response until the master accepts it.

FAQ