RTL Problems / Level 3 · On-Chip Protocols
What You Will Learn
By solving APB Wait-State Handling — PREADY Behavior, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Extend an APB slave to insert exactly 1 wait state (PREADY=0 for one cycle during ACCESS phase) before completing any transfer.
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
Prerequisites: APB protocol, FSM state tracking, PREADY handshake.
Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Name | Dir | Width | Description |
|---|---|---|---|
pclk | input | 1 | APB clock |
preset_n | input | 1 | Active-low reset |
psel | input | 1 | Slave select |
penable | input | 1 | Enable strobe |
pwrite | input | 1 | Write control |
pready | output | 1 | Wait state control (0 = wait, 1 = ready) |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: When a transfer enters ACCESS phase (`psel && penable`), slave drives `pready=0` on the first cycle and `pready=1` on the second cycle.
Synthesis Constraints: Every read or write transaction must take exactly 2 clock cycles in the ACCESS phase (1 wait state).
Architectural Deep Dive & Implementation Walkthrough
Common RTL Designer Pitfalls
['Deasserting `penable` before `pready` goes high, violating AMBA protocol rules.', 'Leaving `wait_done` asserted when entering IDLE.']
Silicon & Hardware Engineering Notes
Wait states allow slow peripherals (e.g. analog ADCs, flash memory, EEPROMs) to interface with high-speed processors without needing asynchronous FIFOs.
Starter RTL Code
module top_module(
input pclk,
input preset_n,
input psel,
input penable,
input pwrite,
output pready
);
// APB slave generating 1 wait-state per transfer
endmodule
Verified Reference Solution
🔒 Reveal Verified Reference RTL Solution
module top_module(
input pclk,
input preset_n,
input psel,
input penable,
input pwrite,
output pready
);
reg wait_done;
always @(posedge pclk or negedge preset_n) begin
if (!preset_n)
wait_done <= 1'b0;
else if (psel && penable)
wait_done <= ~wait_done;
else
wait_done <= 1'b0;
end
assign pready = wait_done;
endmodule
Related RTL Problems in Level 3
- Synchronous RAM — Memory Read/Write — Design a 16-word by 8-bit synchronous RAM (16x8) with synchronous write and synchronous read.
- Single-Port RAM with Write Enable — Memory Control — Implement a 32-word x 8-bit single-port synchronous RAM with read-first (read-during-write) behavior.
- Synchronous FIFO — FIFO Architecture — Design an 8-entry by 8-bit synchronous First-In First-Out (FIFO) buffer with write enable (wr_en), read enable (rd_en), full, and empty flags.
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Frequently Asked Questions
What does APB Wait-State Handling — PREADY Behavior require?
Extend an APB slave to insert exactly 1 wait state (PREADY=0 for one cycle during ACCESS phase) before completing any transfer. Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: memory, fifo, protocols, apb, uart, hard, amba-apb. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of APB Wait-State Handling — PREADY Behavior to assess real-world synthesizability and race-condition awareness.